The application core contains flash memory and RAM that can be used for code and data storage.
The following figure shows how the CPU, network core, and peripherals with EasyDMA can access RAM via the AHB multilayer interconnect. The domain configuration (DCNF) registers can block access from external DMA masters, see DCNF — Domain configuration.
The following table describes the abbreviations used in the Instance, Secure mapping, and DMA security columns of the instantiation table.
Abbreviation | Description |
---|---|
NS | Non-secure - Peripheral is always accessible as a Non-Secure peripheral |
S | Secure - Peripheral is always accessible as a Secure peripheral |
US | User Selectable - A Secure or Non-secure attribute for the peripheral is defined in the SPU |
SPLIT | Both Secure and Non-secure - The same resource is shared by both secure and non-secure code |
NA | Not Applicable - Peripheral has no DMA capability |
NSA | NoSeparateAttribute - Peripheral with DMA and DMA transfer has the same security attribute as assigned to the peripheral |
SA | SeparateAttribute - Peripheral with DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral |
The Secure mapping column in the following table defines configuration capabilities for the Arm® TrustZone® for Armv8-M secure attribute. The DMA security column describes the DMA capabilities of the peripheral.
ID | Base address | Peripheral | Instance | Secure mapping | DMA security | Description | |
---|---|---|---|---|---|---|---|
0 |
0x50000000 |
DCNF |
DCNF : S |
US |
NA |
Domain configuration |
|
0 |
0x50000000 |
FPU |
FPU : S |
US |
NA |
Floating Point unit interrupt control |
|
1 | 0x50001000 | CACHE | CACHE | S | NA |
Cache |
|
3 | 0x50003000 | SPU | SPU | S | NA |
System protection unit |
|
4 |
0x50004000 |
OSCILLATORS |
OSCILLATORS : S |
US |
NA |
Oscillator configuration |
|
4 |
0x50004000 |
REGULATORS |
REGULATORS : S |
US |
NA |
Regulator configuration |
|
5 |
0x50005000 |
CLOCK |
CLOCK : S |
US |
NA |
Clock control |
|
5 |
0x50005000 |
POWER |
POWER : S |
US |
NA |
Power control |
|
5 |
0x50005000 |
RESET |
RESET : S |
US |
NA |
Reset control and status |
|
6 |
0x50006000 |
CTRLAPPERI |
CTRLAP : S |
US |
NSA |
Control access port CPU side |
|
8 |
0x50008000 |
SPIM |
SPIM0 : S |
US |
SA |
SPI master 0 |
|
8 |
0x50008000 |
SPIS |
SPIS0 : S |
US |
SA |
SPI slave 0 |
|
8 |
0x50008000 |
TWIM |
TWIM0 : S |
US |
SA |
Two-wire interface master 0 |
|
8 |
0x50008000 |
TWIS |
TWIS0 : S |
US |
SA |
Two-wire interface slave 0 |
|
8 |
0x50008000 |
UARTE |
UARTE0 : S |
US |
SA |
Universal asynchronous receiver/transmitter with EasyDMA 0 |
|
9 |
0x50009000 |
SPIM |
SPIM1 : S |
US |
SA |
SPI master 1 |
|
9 |
0x50009000 |
SPIS |
SPIS1 : S |
US |
SA |
SPI slave 1 |
|
9 |
0x50009000 |
TWIM |
TWIM1 : S |
US |
SA |
Two-wire interface master 1 |
|
9 |
0x50009000 |
TWIS |
TWIS1 : S |
US |
SA |
Two-wire interface slave 1 |
|
9 |
0x50009000 |
UARTE |
UARTE1 : S |
US |
SA |
Universal asynchronous receiver/transmitter with EasyDMA 1 |
|
10 |
0x5000A000 |
SPIM |
SPIM4 : S |
US |
SA |
SPI master 4 (high-speed) |
|
11 |
0x5000B000 |
SPIM |
SPIM2 : S |
US |
SA |
SPI master 2 |
|
11 |
0x5000B000 |
SPIS |
SPIS2 : S |
US |
SA |
SPI slave 2 |
|
11 |
0x5000B000 |
TWIM |
TWIM2 : S |
US |
SA |
Two-wire interface master 2 |
|
11 |
0x5000B000 |
TWIS |
TWIS2 : S |
US |
SA |
Two-wire interface slave 2 |
|
11 |
0x5000B000 |
UARTE |
UARTE2 : S |
US |
SA |
Universal asynchronous receiver/transmitter with EasyDMA 2 |
|
12 |
0x5000C000 |
SPIM |
SPIM3 : S |
US |
SA |
SPI master 3 |
|
12 |
0x5000C000 |
SPIS |
SPIS3 : S |
US |
SA |
SPI slave 3 |
|
12 |
0x5000C000 |
TWIM |
TWIM3 : S |
US |
SA |
Two-wire interface master 3 |
|
12 |
0x5000C000 |
TWIS |
TWIS3 : S |
US |
SA |
Two-wire interface slave 3 |
|
12 |
0x5000C000 |
UARTE |
UARTE3 : S |
US |
SA |
Universal asynchronous receiver/transmitter with EasyDMA 3 |
|
13 | 0x5000D000 | GPIOTE | GPIOTE0 | S | NA |
GPIO tasks and events |
|
14 |
0x5000E000 |
SAADC |
SAADC : S |
US |
SA |
Successive approximation analog-to-digital converter |
|
15 |
0x5000F000 |
TIMER |
TIMER0 : S |
US |
NA |
Timer 0 |
|
16 |
0x50010000 |
TIMER |
TIMER1 : S |
US |
NA |
Timer 1 |
|
17 |
0x50011000 |
TIMER |
TIMER2 : S |
US |
NA |
Timer 2 |
|
20 |
0x50014000 |
RTC |
RTC0 : S |
US |
NA |
Real time counter 0 |
|
21 |
0x50015000 |
RTC |
RTC1 : S |
US |
NA |
Real time counter 1 |
|
23 |
0x50017000 |
DPPIC |
DPPIC : S |
SPLIT |
NA |
DPPI controller |
|
24 |
0x50018000 |
WDT |
WDT0 : S |
US |
NA |
Watchdog timer 0 |
|
25 |
0x50019000 |
WDT |
WDT1 : S |
US |
NA |
Watchdog timer 1 |
|
26 |
0x5001A000 |
COMP |
COMP : S |
US |
NA |
Comparator |
|
26 |
0x5001A000 |
LPCOMP |
LPCOMP : S |
US |
NA |
Low-power comparator |
|
27 |
0x5001B000 |
EGU |
EGU0 : S |
US |
NA |
Event generator unit 0 |
|
28 |
0x5001C000 |
EGU |
EGU1 : S |
US |
NA |
Event generator unit 1 |
|
29 |
0x5001D000 |
EGU |
EGU2 : S |
US |
NA |
Event generator unit 2 |
|
30 |
0x5001E000 |
EGU |
EGU3 : S |
US |
NA |
Event generator unit 3 |
|
31 |
0x5001F000 |
EGU |
EGU4 : S |
US |
NA |
Event generator unit 4 |
|
32 |
0x50020000 |
EGU |
EGU5 : S |
US |
NA |
Event generator unit 5 |
|
33 |
0x50021000 |
PWM |
PWM0 : S |
US |
SA |
Pulse width modulation unit 0 |
|
34 |
0x50022000 |
PWM |
PWM1 : S |
US |
SA |
Pulse width modulation unit 1 |
|
35 |
0x50023000 |
PWM |
PWM2 : S |
US |
SA |
Pulse width modulation unit 2 |
|
36 |
0x50024000 |
PWM |
PWM3 : S |
US |
SA |
Pulse width modulation unit 3 |
|
38 |
0x50026000 |
PDM |
PDM0 : S |
US |
SA |
Pulse density modulation (digital microphone) interface |
|
40 |
0x50028000 |
I2S |
I2S0 : S |
US |
SA |
Inter-IC sound interface |
|
42 |
0x5002A000 |
IPC |
IPC : S |
US |
NA |
Interprocessor communication |
|
43 |
0x5002B000 |
QSPI |
QSPI : S |
US |
SA |
External memory (quad serial peripheral) interface |
|
45 |
0x5002D000 |
NFCT |
NFCT : S |
US |
SA |
Near field communication tag |
|
47 | 0x4002F000 | GPIOTE | GPIOTE1 | NS | NA |
GPIO tasks and events |
|
48 |
0x50030000 |
MUTEX |
MUTEX : S |
US |
NA |
Mutual exclusive hardware support |
|
51 |
0x50033000 |
QDEC |
QDEC0 : S |
US |
NA |
Quadrature decoder 0 |
|
52 |
0x50034000 |
QDEC |
QDEC1 : S |
US |
NA |
Quadrature decoder 1 |
|
54 |
0x50036000 |
USBD |
USBD : S |
US |
SA |
Universal serial bus device |
|
55 |
0x50037000 |
USBREG |
USBREGULATOR : S |
US |
NA |
USB regulator control |
|
57 |
0x50039000 |
KMU |
KMU : S |
SPLIT |
NA |
Key management unit |
|
57 |
0x50039000 |
NVMC |
NVMC : S |
SPLIT |
NA |
Non-volatile memory controller |
|
66 |
0x50842500 |
GPIO |
P0 : S |
SPLIT |
NA |
General purpose input and output, port 0 |
|
66 |
0x50842800 |
GPIO |
P1 : S |
SPLIT |
NA |
General purpose input and output, port 1 |
|
68 | 0x50844000 | CRYPTOCELL | CRYPTOCELL | S | NSA |
CryptoCell subsystem control interface |
|
129 |
0x50081000 |
VMC |
VMC : S |
US |
NA |
Volatile memory controller |
|
N/A | 0x00F00000 | CACHEDATA | CACHEDATA | S | NA |
Cache data |
|
N/A | 0x00F08000 | CACHEINFO | CACHEINFO | S | NA |
Cache info |
|
N/A | 0x00FF0000 | FICR | FICR | S | NA |
Factory information configuration registers |
|
N/A | 0x00FF8000 | UICR | UICR | S | NA |
User information configuration registers |
|
N/A | 0xE0042000 | CTI | CTI | S | NA |
Cross-trigger interface |
|
N/A | 0xE0080000 | TAD | TAD | S | NA |
Trace and debug control |