QSPI — Quad serial peripheral interface

The QSPI peripheral provides support for communicating with an external flash memory device using SPI.

Listed here are the main features for the QSPI peripheral:

Figure 1. Block diagram

Configuring peripheral

Before any data can be transferred to or from the external flash memory, the peripheral needs to be configured.

  1. Select input/output pins in PSEL.SCK, PSEL.CSN, PSEL.IO0, PSEL.IO1, PSEL.IO2, and PSEL.IO3. See Reference circuitry for the recommended pins.
  2. To ensure stable operation, set the GPIO drive strength to “high drive”. See the GPIO — General purpose input/output chapter for details on how to configure GPIO drive strength.
  3. Configure the interface towards the external flash memory using IFCONFIG0, IFCONFIG1, and ADDRCONF.
  4. Enable the QSPI peripheral and acquire I/O pins using ENABLE.
  5. Activate the external flash memory interface using the ACTIVATE task. The READY event will be generated when the interface has been activated and the external flash memory is ready for access.
Important:

If the IFCONFIG0 register is configured to use the quad mode, the external flash device also needs to be set in the quad mode before any data transfers can take place.

This can be done by sending custom instructions to the external flash device, as described in Sending custom instructions.

Write operation

A write operation to the external flash is configured using the WRITE.DST, WRITE.SRC, and WRITE.CNT registers and started using the WRITESTART task.

The READY event is generated when the transfer is complete.

The QSPI peripheral automatically takes care of splitting DMA transfers into page writes.

Read operation

A read operation from the external flash is configured using the READ.SRC, READ.DST, and READ.CNT registers and started using the READSTART task.

The READY event is generated when the transfer is complete.

Erase operation

Erase of pages/blocks of the external flash is configured using the ERASE.PTR and ERASE.LEN registers and started using the ERASESTART task.

The READY event is generated when the erase operation has been started.

Note that in this case the READY event will not indicate that the erase operation of the flash has been completed, but it only signals that the erase operation has been started. The actual status of the erase operation can normally be read from the external flash using a custom instruction, see Sending custom instructions.

Execute in place

Execute in place (XIP) allows the CPU to execute program code directly from the external flash.

After the external flash has been configured, the CPU can execute code from the external flash by accessing the XIP memory region. See the figure below and Memory for details.

Note that the XIP memory region is read-only, writing to it will result in a bus error.

When accessing the XIP memory region, the start address of this XIP memory region will map to the address XIPOFFSET of the external flash.

Figure 2. XIP memory map
Execute-in-place memory map

Encryption

The contents of an external flash memory can be protected using stream cipher encryption. Encryption can be configured and enabled independently for XIP and EasyDMA, with separate keys and nonce.

Once configured and enabled, the stream cipher operates between the AHB bus and the external flash, encrypting and decrypting data passing through.

Figure Figure 3 shows the stream cipher block with the three configuration registers. The stream cipher uses an AES 128 encryption operation to form the keystream from key, nonce and external memory address. The keystream then combines each 32-bit plaintext digit one at a time with the corresponding digit of the keystream.
Figure 3. Stream cipher

Note: The same nonce and key must be used for both encryption and decryption of the same memory address.

The memory address used for encryption is the external flash memory address and thus independent of XIPOFFSET. This means a second firmware image can be encrypted and written using EasyDMA, then XIPOFFSET set to point to the new firmware image before executing from it.

Note: Stream ciphers are symmetric. They do not differentiate between encrypting or decrypting, reading or writing. Thus, if the contents of a plain text external flash is read when stream cipher is enabled, the data provided to the MCU are encrypted.

Execute in place (XIP)

Stream cipher for QSPI XIP is enabled by
  1. Configuring keys using XIP_ENC.KEY0 through XIP_ENC.KEY3
  2. Configuring nonce using XIP_ENC.NONCE0 through XIP_ENC.NONCE2
  3. Setting XIP_ENC.ENABLE
Any instructions or data read from the XIP interface will now pass through the stream cipher.

EasyDMA

Stream cipher for QSPI EasyDMA is enabled by
  1. Configuring keys using DMA_ENC.KEY0 through DMA_ENC.KEY3
  2. Configuring nonce using DMA_ENC.NONCE0 through DMA_ENC.NONCE2
  3. Setting DMA_ENC.ENABLE
Any data read from, or written to, the external flash over the EasyDMA interface will now pass through the stream cipher.

Sending custom instructions

Custom instructions can be sent to the external flash using the CINSTRCONF, CINSTRDAT0, and CINSTRDAT1 registers. It is possible to send an instruction consisting of a one-byte opcode and up to 8 bytes of additional data and to read its response.

A custom instruction is prepared by first writing the data to be sent to CINSTRDAT0 and CINSTRDAT1 before writing the opcode and other configurations to the CINSTRCONF register.

The custom instruction is sent when the CINSTRCONF register is written and it is always sent on a single data line SPI interface.

The READY event will be generated when the custom instruction has been sent.

After a custom instruction has been sent, the CINSTRDAT0 and CINSTRDAT1 will contain the response bytes from the custom instruction.

Data of custom instructions are not part of the stream cipher encryption.

Figure 4. Sending custom instruction

Long frame mode

The LFEN and LFSTOP fields in the CINSTRCONF control the operation of the custom instruction long frame mode. The long frame mode is a mechanism that permits arbitrary byte length custom instructions. While in long frame mode a long custom instruction sequence is split in multiple writes to the CINSTRDAT0 and CINSTRDAT1 registers.

To enable the long frame mode every write to the CINSTRCONF register must have the LFEN field set to 1. The contents of the OPCODE field will be transmitted after the first write to CINSTRCONF and will be omitted in every subsequent write to this register. For subsequent writes the number of data bytes as specified in the LENGTH field are transferred (that is the value of LENGTH - 1 data bytes). The values of the LIO2 and LIO3 fields are set in the first write to CINSTRCONF and will apply for the entire custom instruction transmission until the long frame is finalized.

To finalize a long frame transmission, the LFSTOP field in CINSTRCONF must be set to 1 in the last write to this register.

Deep power-down mode

The external flash memory can be put in deep power-down mode (DPM) to minimize its current consumption when there is no need to access the memory.

DPM is enabled in the IFCONFIG0 register and configured in the DPMDUR register. The DPM status of the external memory can be read in the STATUS register. The DPMDUR register has to be configured according to the external flash specification to get the information in the STATUS register and the timing of the READY event correct.

Entering/exiting DPM is controlled using the IFCONFIG1 register.

Instruction set

The table below shows the instruction set being used by the QSPI peripheral when communicating with an external flash device.

Table 1. Instruction set
Instruction Opcode Description
WREN 0x06 Write enable
RDSR 0x05 Read status register
WRSR 0x01 Write status register
FASTREAD 0x0B Read bytes at higher speed
READ2O 0x3B Dual-read output
READ2IO 0xBB Dual-read input/output
READ4O 0x6B Quad-read output
READ4IO 0xEB Quad-read input/output
PP 0x02 Page program
PP2O 0xA2 Dual-page program output
PP4O 0x32 Quad-page program output
PP4IO 0x38 Quad-page program input/output
SE 0x20 Sector erase
BE 0xD8 Block erase
CE 0xC7 Chip erase
DP 0xB9 Enter deep power-down mode
DPE 0xAB Exit deep power-down mode
EN4B Specified in the ADDRCONF register Enable 32 bit address mode

Interface description

Figure 5. 24-bit FASTREAD, SPIMODE = MODE0
24-bit FASTREAD, SPIMODE = MODE0

Figure 6. 24-bit READ2O (dual-read output), SPIMODE = MODE0
24-bit READ2O (dual-read output), SPIMODE = MODE0

Figure 7. 24-bit READ2IO (dual read input/output), SPIMODE = MODE0
24-bit READ2IO (dual read input/output), SPIMODE = MODE0

Figure 8. 24-bit READ4O (quad-read output), SPIMODE = MODE0
24-bit READ4O (quad-read output), SPIMODE = MODE0

Figure 9. 24-bit READ4IO (quad-read input/output), SPIMODE = MODE0
24-bit READ4IO (quad-read input/output), SPIMODE = MODE0

Figure 10. 24-bit PP (page program), SPIMODE = MODE0
24-bit PP (page program), SPIMODE = MODE0

Figure 11. 24-bit PP2O (dual-page program output), SPIMODE = MODE0
24-bit PP2O (dual-page program output), SPIMODE = MODE0

Figure 12. 24-bit PP4O (quad page program output), SPIMODE = MODE0
24-bit PP4O (quad page program output), SPIMODE = MODE0

Figure 13. 24-bit PP4IO (quad page program input/output), SPIMODE = MODE0
24-bit PP4IO (quad page program input/output), SPIMODE = MODE0

Figure 14. 32-bit FASTREAD, SPIMODE = MODE0
32-bit FASTREAD, SPIMODE = MODE0

Figure 15. 32-bit READ2O (dual-read output), SPIMODE = MODE0
32-bit READ2O (dual-read output), SPIMODE = MODE0

Figure 16. 32-bit READ2IO (dual read input/output), SPIMODE = MODE0
32-bit READ2IO (dual read input/output), SPIMODE = MODE0

Figure 17. 32-bit READ4O (quad-read output), SPIMODE = MODE0
32-bit READ4O (quad-read output), SPIMODE = MODE0

Figure 18. 32-bit READ4IO (quad-read input/output), SPIMODE = MODE0
2-bit READ4IO (quad-read input/output), SPIMODE = MODE0

Figure 19. 32-bit PP (page program), SPIMODE = MODE0
32-bit PP (page program), SPIMODE = MODE0

Figure 20. 32-bit PP2O (dual-page program output), SPIMODE = MODE0
32-bit PP2O (dual-page program output), SPIMODE = MODE0

Figure 21. 32-bit PP4O (quad-page program output), SPIMODE = MODE0
32-bit PP4O (quad-page program output), SPIMODE = MODE0

Figure 22. 32-bit PP4IO (quad page program input/output), SPIMODE = MODE0
32-bit PP4IO (quad page program input/output), SPIMODE = MODE0

Registers

Table 2. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x5002B000
0x4002B000

APPLICATION QSPI

QSPI : S
QSPI : NS

US

SA

External memory (quad serial peripheral) interface

Supports 192 MHz and 96 MHz PCLK192M frequency

 
Table 3. Register overview
Register Offset Security Description
TASKS_ACTIVATE 0x000  

Activate QSPI interface

 
TASKS_READSTART 0x004  

Start transfer from external flash memory to internal RAM

 
TASKS_WRITESTART 0x008  

Start transfer from internal RAM to external flash memory

 
TASKS_ERASESTART 0x00C  

Start external flash memory erase operation

 
TASKS_DEACTIVATE 0x010  

Deactivate QSPI interface

 
SUBSCRIBE_ACTIVATE 0x080  

Subscribe configuration for task ACTIVATE

 
SUBSCRIBE_READSTART 0x084  

Subscribe configuration for task READSTART

 
SUBSCRIBE_WRITESTART 0x088  

Subscribe configuration for task WRITESTART

 
SUBSCRIBE_ERASESTART 0x08C  

Subscribe configuration for task ERASESTART

 
SUBSCRIBE_DEACTIVATE 0x090  

Subscribe configuration for task DEACTIVATE

 
EVENTS_READY 0x100  

QSPI peripheral is ready. This event will be generated as a response to any QSPI task.

 
PUBLISH_READY 0x180  

Publish configuration for event READY

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
ENABLE 0x500  

Enable QSPI peripheral and acquire the pins selected in PSELn registers

 
READ.SRC 0x504  

Flash memory source address

 
READ.DST 0x508  

RAM destination address

 
READ.CNT 0x50C  

Read transfer length

 
WRITE.DST 0x510  

Flash destination address

 
WRITE.SRC 0x514  

RAM source address

 
WRITE.CNT 0x518  

Write transfer length

 
ERASE.PTR 0x51C  

Start address of flash block to be erased

 
ERASE.LEN 0x520  

Size of block to be erased.

 
PSEL.SCK 0x524  

Pin select for serial clock SCK

 
PSEL.CSN 0x528  

Pin select for chip select signal CSN.

 
PSEL.IO0 0x530  

Pin select for serial data MOSI/IO0.

 
PSEL.IO1 0x534  

Pin select for serial data MISO/IO1.

 
PSEL.IO2 0x538  

Pin select for serial data IO2.

 
PSEL.IO3 0x53C  

Pin select for serial data IO3.

 
XIPOFFSET 0x540  

Address offset into the external memory for Execute in Place operation.

 
IFCONFIG0 0x544  

Interface configuration.

 
XIPEN 0x54C  

Enable Execute in Place operation.

 
XIP_ENC.KEY0 0x560  

Bits 31:0 of XIP AES KEY

 
XIP_ENC.KEY1 0x564  

Bits 63:32 of XIP AES KEY

 
XIP_ENC.KEY2 0x568  

Bits 95:64 of XIP AES KEY

 
XIP_ENC.KEY3 0x56C  

Bits 127:96 of XIP AES KEY

 
XIP_ENC.NONCE0 0x570  

Bits 31:0 of XIP NONCE

 
XIP_ENC.NONCE1 0x574  

Bits 63:32 of XIP NONCE

 
XIP_ENC.NONCE2 0x578  

Bits 95:64 of XIP NONCE

 
XIP_ENC.ENABLE 0x57C  

Enable stream cipher for XIP

 
DMA_ENC.KEY0 0x580  

Bits 31:0 of DMA AES KEY

 
DMA_ENC.KEY1 0x584  

Bits 63:32 of DMA AES KEY

 
DMA_ENC.KEY2 0x588  

Bits 95:64 of DMA AES KEY

 
DMA_ENC.KEY3 0x58C  

Bits 127:96 of DMA AES KEY

 
DMA_ENC.NONCE0 0x590  

Bits 31:0 of DMA NONCE

 
DMA_ENC.NONCE1 0x594  

Bits 63:32 of DMA NONCE

 
DMA_ENC.NONCE2 0x598  

Bits 95:64 of DMA NONCE

 
DMA_ENC.ENABLE 0x59C  

Enable stream cipher for XIP

 
IFCONFIG1 0x600  

Interface configuration.

 
STATUS 0x604  

Status register.

 
DPMDUR 0x614  

Set the duration required to enter/exit deep power-down mode (DPM).

 
ADDRCONF 0x624  

Extended address configuration.

 
CINSTRCONF 0x634  

Custom instruction configuration register.

 
CINSTRDAT0 0x638  

Custom instruction data register 0.

 
CINSTRDAT1 0x63C  

Custom instruction data register 1.

 
IFTIMING 0x640  

SPI interface timing.

 

TASKS_ACTIVATE

Address offset: 0x000

Activate QSPI interface

Triggering this task activates the external flash memory interface and initiates communication with the external memory. The READY event is generated when the activation has been completed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_ACTIVATE

   

Activate QSPI interface

Triggering this task activates the external flash memory interface and initiates communication with the external memory. The READY event is generated when the activation has been completed.

     

Trigger

1

Trigger task

TASKS_READSTART

Address offset: 0x004

Start transfer from external flash memory to internal RAM

Start transfer from external flash memory to internal RAM. The READY event will be generated when transfer is complete.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_READSTART

   

Start transfer from external flash memory to internal RAM

Start transfer from external flash memory to internal RAM. The READY event will be generated when transfer is complete.

     

Trigger

1

Trigger task

TASKS_WRITESTART

Address offset: 0x008

Start transfer from internal RAM to external flash memory

Start transfer from internal RAM to external flash memory. The READY event will be generated when transfer is complete.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_WRITESTART

   

Start transfer from internal RAM to external flash memory

Start transfer from internal RAM to external flash memory. The READY event will be generated when transfer is complete.

     

Trigger

1

Trigger task

TASKS_ERASESTART

Address offset: 0x00C

Start external flash memory erase operation

Start external flash memory erase operation. The READY event will be generated when the erase operation has been started. Note, generation of the READY event does not imply that the erase operation is completed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_ERASESTART

   

Start external flash memory erase operation

Start external flash memory erase operation. The READY event will be generated when the erase operation has been started. Note, generation of the READY event does not imply that the erase operation is completed.

     

Trigger

1

Trigger task

TASKS_DEACTIVATE

Address offset: 0x010

Deactivate QSPI interface

Deactivate QSPI interface. This task might be needed to optimize current consumption in case there are any added current consumption when QSPI interface is activated, but idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_DEACTIVATE

   

Deactivate QSPI interface

Deactivate QSPI interface. This task might be needed to optimize current consumption in case there are any added current consumption when QSPI interface is activated, but idle.

     

Trigger

1

Trigger task

SUBSCRIBE_ACTIVATE

Address offset: 0x080

Subscribe configuration for task ACTIVATE

Triggering this task activates the external flash memory interface and initiates communication with the external memory. The READY event is generated when the activation has been completed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task ACTIVATE will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_READSTART

Address offset: 0x084

Subscribe configuration for task READSTART

Start transfer from external flash memory to internal RAM. The READY event will be generated when transfer is complete.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task READSTART will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_WRITESTART

Address offset: 0x088

Subscribe configuration for task WRITESTART

Start transfer from internal RAM to external flash memory. The READY event will be generated when transfer is complete.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task WRITESTART will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_ERASESTART

Address offset: 0x08C

Subscribe configuration for task ERASESTART

Start external flash memory erase operation. The READY event will be generated when the erase operation has been started. Note, generation of the READY event does not imply that the erase operation is completed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task ERASESTART will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_DEACTIVATE

Address offset: 0x090

Subscribe configuration for task DEACTIVATE

Deactivate QSPI interface. This task might be needed to optimize current consumption in case there are any added current consumption when QSPI interface is activated, but idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task DEACTIVATE will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_READY

Address offset: 0x100

QSPI peripheral is ready. This event will be generated as a response to any QSPI task.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_READY

   

QSPI peripheral is ready. This event will be generated as a response to any QSPI task.

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_READY

Address offset: 0x180

Publish configuration for event READY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event READY will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY

   

Enable or disable interrupt for event READY

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY

   

Write '1' to enable interrupt for event READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY

   

Write '1' to disable interrupt for event READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

ENABLE

Address offset: 0x500

Enable QSPI peripheral and acquire the pins selected in PSELn registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ENABLE

   

Enable or disable QSPI

     

Disabled

0

Disable QSPI

     

Enabled

1

Enable QSPI

READ.SRC

Address offset: 0x504

Flash memory source address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

SRC

   

Word-aligned flash memory source address.

READ.DST

Address offset: 0x508

RAM destination address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

DST

   

Word-aligned RAM destination address.

READ.CNT

Address offset: 0x50C

Read transfer length

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                       A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CNT

 

Read transfer length in number of bytes. The length must be a multiple of 4 bytes.

WRITE.DST

Address offset: 0x510

Flash destination address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

DST

   

Word-aligned flash destination address.

WRITE.SRC

Address offset: 0x514

RAM source address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

SRC

   

Word-aligned RAM source address.

WRITE.CNT

Address offset: 0x518

Write transfer length

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                       A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CNT

 

Write transfer length in number of bytes. The length must be a multiple of 4 bytes.

ERASE.PTR

Address offset: 0x51C

Start address of flash block to be erased

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

PTR

   

Word-aligned start address of block to be erased.

ERASE.LEN

Address offset: 0x520

Size of block to be erased.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

LEN

   

LEN

     

4KB

0

Erase 4 kB block (flash command 0x20)

     

64KB

1

Erase 64 kB block (flash command 0xD8)

     

All

2

Erase all (flash command 0xC7)

PSEL.SCK

Address offset: 0x524

Pin select for serial clock SCK

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.CSN

Address offset: 0x528

Pin select for chip select signal CSN.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.IO0

Address offset: 0x530

Pin select for serial data MOSI/IO0.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.IO1

Address offset: 0x534

Pin select for serial data MISO/IO1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.IO2

Address offset: 0x538

Pin select for serial data IO2.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.IO3

Address offset: 0x53C

Pin select for serial data IO3.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

PORT

 

[0..1]

Port number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

XIPOFFSET

Address offset: 0x540

Address offset into the external memory for Execute in Place operation.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

XIPOFFSET

   

Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4.

IFCONFIG0

Address offset: 0x544

Interface configuration.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                       G D C B B B A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READOC

   

Configure number of data lines and opcode used for reading.

     

FASTREAD

0

Single data line SPI. FAST_READ (opcode 0x0B).

     

READ2O

1

Dual data line SPI. READ2O (opcode 0x3B).

     

READ2IO

2

Dual data line SPI. READ2IO (opcode 0xBB).

     

READ4O

3

Quad data line SPI. READ4O (opcode 0x6B).

     

READ4IO

4

Quad data line SPI. READ4IO (opcode 0xEB).

B RW

WRITEOC

   

Configure number of data lines and opcode used for writing.

     

PP

0

Single data line SPI. PP (opcode 0x02).

     

PP2O

1

Dual data line SPI. PP2O (opcode 0xA2).

     

PP4O

2

Quad data line SPI. PP4O (opcode 0x32).

     

PP4IO

3

Quad data line SPI. PP4IO (opcode 0x38).

C RW

ADDRMODE

   

Addressing mode.

     

24BIT

0

24-bit addressing.

     

32BIT

1

32-bit addressing.

D RW

DPMENABLE

   

Enable deep power-down mode (DPM) feature.

     

Disable

0

Disable DPM feature.

     

Enable

1

Enable DPM feature.

G RW

PPSIZE

   

Page size for commands PP, PP2O, PP4O and PP4IO.

     

256Bytes

0

256 bytes.

     

512Bytes

1

512 bytes.

XIPEN

Address offset: 0x54C

Enable Execute in Place operation.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A RW

XIPEN

   

Enable XIP AHB Slave interface and access to XIP memory range

When disabled, access to external memory is only available through EasyDMA and custom instructions. Access to disabled XIP interface will cause a Bus Error, and the value read is all zeros.

     

Disable

0

Disable XIP interface

     

Enable

1

Enable XIP interface

XIP_ENC.KEY0

Address offset: 0x560

Bits 31:0 of XIP AES KEY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

KEY0

   

Bits 31:0 of XIP AES KEY

XIP_ENC.KEY1

Address offset: 0x564

Bits 63:32 of XIP AES KEY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

KEY1

   

Bits 63:32 of XIP AES KEY

XIP_ENC.KEY2

Address offset: 0x568

Bits 95:64 of XIP AES KEY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0