Product overview

nRF5340 is a wireless, ultra-low power multicore System on Chip (SoC), integrating two fully programmable Arm® Cortex®-M33 processors, advanced security features, a range of peripherals, and a multiprotocol 2.4 GHz transceiver. The transceiver supports Bluetooth® Low Energy, ANT™, and IEEE 802.15.4 for Thread and Zigbee protocols. It also allows the implementation of proprietary 2.4 GHz protocols.

The two Arm Cortex-M33 processors share the power, clock, and peripheral architecture with Nordic Semiconductor nRF51, nRF52, and nRF91 Series of SoCs, ensuring minimal porting efforts. The application core is a full-featured Arm Cortex-M33 processor including DSP instructions and FPU, running at up to 128 MHz with 1 MB of flash and 512 kB of RAM. The option to run the application processor at 64 MHz allows the CPU to increase energy efficiency. The network core is an Arm Cortex-M33 processor with a reduced feature set, designed for ultra-low power operation. It runs at a fixed 64 MHz frequency and contains 256 kB of flash and 64 kB of RAM.

The peripheral set offers a variety of analog and digital functionality enabling single-chip implementation of a wide range of applications. Arm TrustZone® technology, Arm CryptoCell™-312, and supporting blocks for system protection and key management are embedded for the advanced security needed for IoT applications.

Block diagram

The block diagram illustrates the overall system. More detailed diagrams of the two cores, including pins and EasyDMA connectivity, can be found in Block diagram and Block diagram.

Figure 1. Simplified block diagram

Memory

The nRF5340 SoC contains two processor cores, each with flash memory and RAM that can be used for code and data storage.

Table 1. nRF5340 memory configuration
Core	RAM	Flash
Application core	512 kB, arranged as follows: 256 kB CPU single-cycle RAM 256 kB of additional RAM	1024 kB in 4 kB pages
Network core	64 kB total	256 kB in 2 kB pages

All memory and registers are found in the same address space, as shown in Memory map. This includes the two blocks of 256 kB RAM, which are accessible in the memory map as one contiguous 512 kB block of RAM. The first 256 kB block of RAM has single-cycle access time from the CPU, while up to four CPU cycles additional latency occurs when accessing the additional 256 kB block of RAM.

The application core memory is mapped to the network core memory map. This means that the network core CPU can access and use the application core memory for shared memory communication. The application core can restrict network core access through the domain configuration (DCNF) PROTECT registers, see DCNF — Domain configuration. Access to secure memory or peripherals as defined by the SPU — System protection unit is also prevented when the network core is marked as non-secure in an application using TrustZone technology.

Note: The EasyDMA masters of the network core peripherals cannot access the application core RAM. The network core processor cannot execute code directly from the application core flash or access QSPI XIP memories.

Figure 2. Memory map

RAM — Random access memory

RAM can be read and written an unlimited number of times.

Each RAM AHB slave within a core is connected to one or more RAM sections that has separate power control for System ON and System OFF mode operation. For details, see VMC — Volatile memory controller.

Flash — Non-volatile memory

Flash memory can be read an unlimited number of times by the CPU, but is restricted in the number of times it can be written to or erased. Flash memory is also restricted in how it can be written.

Writing to flash memory is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile memory controller.

Flash memory is divided in pages, as listed in nRF5340 memory configuration.

XIP — Execute in place

Execute in Place (XIP) allows the application core to execute program code directly from the external flash memory device using the Quad serial peripheral interface (QSPI). The external flash memory supports on-the-fly encryption and decryption.

For details, see QSPI — Quad serial peripheral interface.

Access latency

When accessing memories or peripherals across bus bridges, additional access latency will occur. An example of this is when the network core accesses the application core memory or peripherals.