VMC — Volatile memory controller

The VMC provides power control of RAM blocks.

Each of the available RAM blocks, which each may contain multiple RAM sections, can power up and down independently in both System ON and System OFF mode, using the RAM[n] registers. See Memory chapter for more information about RAM blocks and sections.

RAM power states

In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding register RAM[n].POWER (n=0..7).

In System ON, retention and accessibility for a RAM section is configured in the RETENTION and POWER fields of the corresponding register RAM[n].POWER (n=0..7).

The following table summarizes the behavior of these registers.

Table 1. RAM section configuration. x = don't care.
Configuration     RAM section status  
System on/off RAM[n].POWER.POWER RAM[n].POWER.RETENTION Accessible Retained
Off x Off No No
Off x On No Yes
On Off Off No No
On Off1 On No Yes
On On x Yes Yes

The advantage of not retaining RAM contents is that the overall current consumption is reduced.

See chapter Memory for more information on RAM sections.

Registers

Table 2. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50081000
0x40081000

APPLICATION VMC

VMC : S
VMC : NS

US

NA

Volatile memory controller

   
0x41081000 NETWORK VMC VMC NS NA

Volatile memory controller

4 RAM slaves implemented

4 RAM slaves implemented

 
Table 3. Register overview
Register Offset Security Description
RAM[n].POWER 0x600  

RAM[n] power control register

 
RAM[n].POWERSET 0x604  

RAM[n] power control set register

 
RAM[n].POWERCLR 0x608  

RAM[n] power control clear register

 

RAM[n].POWER (n=0..7)

Address offset: 0x600 + (n × 0x10)

RAM[n] power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-P RW

S[i]POWER (i=0..15)

   

Keep RAM section Si of RAM[n] on or off in System ON mode

All RAM sections will be switched off in System OFF mode

     

Off

0

Off

     

On

1

On

Q-f RW

S[i]RETENTION (i=0..15)

   

Keep retention on RAM section Si of RAM[n] when RAM section is switched off

     

Off

0

Off

     

On

1

On

RAM[n].POWERSET (n=0..7)

Address offset: 0x604 + (n × 0x10)

RAM[n] power control set register

When read, this register will return the value of the RAM[n].POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-P RW

S[i]POWER (i=0..15)

   

Keep RAM section Si of RAM[n] on or off in System ON mode

     

On

1

On

Q-f RW

S[i]RETENTION (i=0..15)

   

Keep retention on RAM section Si of RAM[n] when RAM section is switched off

     

On

1

On

RAM[n].POWERCLR (n=0..7)

Address offset: 0x608 + (n × 0x10)

RAM[n] power control clear register

When read, this register will return the value of the RAM[n].POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-P RW

S[i]POWER (i=0..15)

   

Keep RAM section Si of RAM[n] on or off in System ON mode

     

Off

1

Off

Q-f RW

S[i]RETENTION (i=0..15)

   

Keep retention on RAM section Si of RAM[n] when RAM section is switched off

     

Off

1

Off

1 Not useful setting. RAM section power off gives negligible reduction in current consumption when retention is on.

This document was last updated on
2019-12-09.
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