Peripherals

nRF5340 is made up of two cores, each with their own peripherals.

The application core peripherals are found in Instantiation and the network core peripherals are found in Instantiation. The application core peripherals are accessible from the network core, but the network core peripherals are not accessible from the application core. For further details, see Memory.

Some peripheral instances have differing configurations, such as some TIMER instances which have more capture and compare channels implemented than others. These differences are noted in the Configuration column of the peripheral's instantiation table.

Peripheral interface
Peripherals are controlled by the CPU through configuration registers, as well as task and event registers. Task registers are inputs, enabling the CPU and other peripherals to initiate a functionality. Event registers are outputs, enabling a peripheral to trigger tasks in other peripherals and/or the CPU by tying events to CPU interrupts.
EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
ACL — Access control lists
The Access control lists (ACL) peripheral is designed to assign and enforce access permissions to different regions of the on-chip flash memory map.
AAR — Accelerated address resolver
Accelerated address resolver is a cryptographic support function for implementing the Resolvable Private Address Resolution procedure described in Bluetooth Core Specification. Resolvable Private Address generation should be achieved using ECB and is not supported by AAR.
CCM — AES CCM mode encryption
Counter with cipher block chaining - message authentication code (CCM) mode is an authenticated encryption algorithm designed to provide both authentication and confidentiality during data transfer.
COMP — Comparator
The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can be derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on the operation mode of the comparator.
CRYPTOCELL — Arm TrustZone CryptoCell 312
Arm® TrustZone® CryptoCell 312 (CRYPTOCELL) is a security subsystem providing root of trust (RoT) and cryptographic services for a device.
DCNF — Domain configuration
The domain configuration (DCNF) module provides a way to identify the CPU by its CPU ID in the device (CPUID). It also provides protection of the AHB multilayer interconnect (AMLI).
DPPI — Distributed programmable peripheral interconnect
The distributed programmable peripheral interconnect (DPPI) enables peripherals to interact autonomously with each other by using tasks and events, without any intervention from the CPU. DPPI allows precise synchronization between peripherals when real-time application constraints exist, and eliminates the need for CPU involvement to implement behavior which can be predefined using the DPPI.
ECB — AES electronic codebook mode encryption
The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption).
EGU — Event generator unit
Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware (by PPI). This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible.
FPU — Floating point unit (FPU) exceptions
The Arm® Cortex®-M33 has FPU signals that indicate mathematical errors that cause floating-point exceptions.
GPIO — General purpose input/output
The general purpose input/output pins (GPIOs) are grouped as one or more ports with each port having up to 32 GPIOs.
GPIOTE — GPIO tasks and events
The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and events. Each GPIOTE channel can be assigned to one pin.
I2S — Inter-IC sound interface
The I²S (Inter-IC Sound) module, supports the original two-channel I²S format, and left- or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.
IPC — Interprocessor communication
The interprocessor communication (IPC) peripheral is used to send and receive events between MCUs in the system.
KMU — Key management unit
The key management unit (KMU) enforces access policies to a subset region of user information configuration register (UICR). This subset region is used for storing cryptographic key values inside the key slots, which the CPU has no access to.
LPCOMP — Low-power comparator
Low-power comparator (LPCOMP) compares an input voltage against a reference voltage.
MUTEX — Mutual exclusive peripheral
The MUTEX peripheral uses mutual exclusion to support locking a resource that is shared between different CPUs in the system. The shared resource can only be used by one of these cores during the duration that it is locked.
NFCT — Near field communication tag
The NFCT peripheral is an implementation of an NFC Forum compliant listening device NFC-A.
NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the user information configuration register (UICR).
PDM — Pulse density modulation interface
The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports single-channel or dual-channel (left and right) data input. Data is transferred directly to RAM buffers using EasyDMA.
PWM — Pulse width modulation
The pulse width modulation (PWM) module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs.
QDEC — Quadrature decoder
The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors.
QSPI — Quad serial peripheral interface
The QSPI peripheral provides support for communicating with an external flash memory device using SPI.
RADIO — 2.4 GHz radio
The 2.4 GHz radio transceiver is compatible with multiple radio standards such as Bluetooth® Low Energy, IEEE 802.15.4, and Nordic's proprietary modes.
RNG — Random number generator
The Random number generator (RNG) generates true non-deterministic random numbers based on internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value.
RTC — Real-time counter
The real-time counter (RTC) module provides a generic, low-power timer on the low frequency clock source (LFCLK).
SAADC — Successive approximation analog-to-digital converter
SAADC is a differential successive approximation register (SAR) analog-to-digital converter (ADC).
SPIM — Serial peripheral interface master with EasyDMA
The SPI master can communicate with multiple SPI slaves using individual chip select signals for each slave.
SPIS — Serial peripheral interface slave with EasyDMA
SPI slave (SPIS) is implemented with EasyDMA support for ultra-low power serial communication from an external SPI master. EasyDMA in conjunction with hardware-based semaphore mechanisms removes all real-time requirements associated with controlling the SPI slave from a low priority CPU execution context.
SPU — System protection unit
SPU is the central point in the system to control access to memories, peripherals and other resources.
SWI — Software interrupts
A set of interrupts have been reserved for use as software interrupts.
TEMP — Temperature sensor
The temperature sensor measures die temperature over the temperature range of the device. Linearity compensation can be implemented if required by the application.
TIMER — Timer/counter
This peripheral is a general purpose timer allowing time intervals to be defined by user input. It can operate in two modes: Timer mode and Counter mode.
TWIM — I2C compatible two-wire interface master with EasyDMA
TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple slave devices connected to the same bus.
TWIS — I2C compatible two-wire interface slave with EasyDMA
TWI slave with EasyDMA (TWIS) is a two-wire half-duplex slave which can communicate with a master device connected to the same bus.
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication. Built-in flow control (CTS, RTS) is supported in hardware at a rate up to 1 Mbps and EasyDMA data transfer to and from RAM.
USBD — Universal serial bus device
The USB device (USBD) controller implements a full speed USB device function that meets 2.0 revision of the USB specification.
VMC — Volatile memory controller
VMC provides power control for RAM blocks.
WDT — Watchdog timer
The countdown watchdog timer (WDT) uses the low-frequency clock source (LFCLK) and offers configurable and robust protection against application lock-up.

Parent topic: nRF5340 Product Specification

This document was last updated on 2023-12-04.
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