GPIO — General purpose input/output

GPIO pins of the system can be allocated among the cores, peripherals with dedicated pins, or subsystems such as trace and debug.

The pins of the system are listed in Pin assignments.

By default, all pins are assigned to the application core. The application core's MCUSEL bitfield in register PIN_CNF[n] (n=0..31) (Retained) controls the allocation of the pins into cores, peripherals and the TaD subsystem.

The pin's state, being either an output, input, or analog, can only be controlled and observed by the core for which the pin was allocated. Reading a pin that is not allocated to the current core will return zero, and writes will be ignored. If a pin is allocated to a subsystem that cannot access it, the pin stays under control of the application core's GPIO peripheral.

The GPIO peripheral of any core has its own set of registers that can be read and written independently, but they only affect a pin when it has been allocated to this core. Reading the GPIO peripheral registers of one core does not reveal the register contents of a different core.

The following figure illustrates how to assign a pin to a core, to a peripheral that has dedicated pins, or a subsystem such as trace and debug.

Figure 2. Pin allocation in multiple-core system

Also note that when a pin p is not assigned to the application core, the application core's GPIO LATCH register, PIN_CNF[p].MCUSEL bitfield, and PIN_CNF[p].SENSE bitfield is prevented. For these, any write operations are ignored, and any read operation will return 0.

The GPIO port peripheral implements up to 32 pins, PIN0 through PIN31. Each of these pins can be individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be configured through these registers:

• Direction
• Drive strength
• Enabling of pull-up and pull-down resistors
• Pin sensing
• Input buffer disconnect
• Analog input (for selected pins)

The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is not used as an input, see GPIO port and the GPIO pin details. Inputs must be connected to get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details. The assignment of the analog pins can be found in Pin assignments.

The drive strength is configured using the DRIVE field of register PIN_CNF[n] (n=0..31) (Retained). Some pins may not support every drive configuration, see Pin assignments for more information.

Pins sensitivity can be individually configured, through the SENSE field in the PIN_CNF[n] register, to detect either a high level or a low level on their input.

When the correct level is detected on any such configured pin, the sense mechanism will set the DETECT signal high. Each pin has a separate DETECT signal. Default behavior, defined by the DETECTMODE register, is that the DETECT signals from all pins in the GPIO port are combined into one common DETECT signal that is routed throughout the system, which then can be utilized by other peripherals. This mechanism is functional in both System ON and System OFF modes.

DETECTMODE and DETECTMODE_SEC are provided to handle secure and non-secure pins. DETECTMODE_SEC register is available to control the behavior associated to pin marked as secure, while the DETECTMODE register is restricted to pin marked as non-secure. Please refer to GPIO security for more details.

Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. The DETECT signal will go high immediately if the SENSE condition configured in the PIN_CNF registers is met when the sense mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling the sense mechanism.

The DETECT signal is also used by power and clock management system to exit from System OFF mode, and by GPIOTE to generate the PORT event. In addition GPIOTE_SEC is used for PORT event related to secure pins). See POWER — Power control and GPIOTE — GPIO tasks and events for more information about how the DETECT signal is used.

When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register. For example, when the PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'. If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared. The LATCH register will only be cleared if the CPU explicitly clears it by writing a '1' to the bit that shall be cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.

The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT signal will be set low when all bits in the LATCH register are successfully cleared to '0'.

If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the LATCH registers, a rising edge will be generated on the LDETECT signal. This is illustrated in DETECT signal behavior.

The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the DETECTMODE register it is possible to change from default behavior to DETECT signal being derived directly from the LDETECT signal instead. See GPIO port and the GPIO pin details. DETECT signal behavior illustrates the DETECT signal behavior for these two alternatives.

Figure 3. DETECT signal behavior

The general purpose input/output (GPIO) peripheral is implemented as a split-security peripheral. If marked as non-secure, it can be accessed by both secure and non-secure accesses but will behave differently depending on the access type.

A non-secure peripheral access will only be able to configure and control pins defined as non-secure in the system protection unit (SPU) GPIOPORT.PERM[] register(s).

A non-secure access to a register or a bitfield controlling a pin marked as secure in GPIO.PERM[] register(s) will be ignored. Write access will have no effect and read access will return a zero value.

The GPIO.DETECTMODE and GPIO.DETECTMODE_SEC registers are handled differently than the other registers mentioned before. When accessed by a secure access, the DETECTMODE_SEC register control the source for the DETECT_SEC signal for the pins marked as secure. When accessed by a non-secure access, the DETECTMODE_SEC is read as zero and write accesses are ignored. The GPIO.DETECTMODE register controls the source for the DETECT_NSEC signal for the pins defined as non-secure.

The DETECT_NSEC signal is routed to the GPIOTE peripheral, allowing generation of events and interrupts from pins marked as non-secure. The DETECT_SEC signal is routed to the GPIOTESEC peripheral, allowing generation of events and interrupts from pins marked as secure. Principle of direct pin access illustrates how the DETECT_NSEC and DETECT_SEC signals are generated from the GPIO PIN[].DETECT signals.

Figure 4. Principle of direct pin access