POWER — Power control

The POWER peripheral provides an interface for the power and clock subsystem for task, event, and interrupt related settings.

Each core has its own POWER peripheral that is responsible for requesting resources from the power and clock subsystem. The power and clock subsystem ensure that the power mode with the proper latency settings is selected when requested by an instance of the POWER peripheral. This means that for the core, the Constant latency mode is prioritized over Low-power mode. For an overview of power modes, see Power submodes.

The POFWARN event is a system level event that enables each core to react quickly if there is a power failure. The power-fail comparator must be configured and enabled in order to receive the event, see Power-fail comparator for more information.

Power control of the RAM blocks is controlled by the Volatile memory controller (VMC), see VMC — Volatile memory controller.

Note: Registers INTEN, INTENSET, and INTENCLR are shared between the POWER and CLOCK peripherals.

Registers

Table 1. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50005000
0x40005000

 APPLICATION POWER

POWER : S
POWER : NS

US

 NA

Power control

    
0x41005000 NETWORK POWER POWER NS NA

Power control

    
Table 2. Register overview
Register Offset Security Description
TASKS_CONSTLAT 0x78  

Enable Constant Latency mode

  
TASKS_LOWPWR 0x7C  

Enable Low-Power mode (variable latency)

  
SUBSCRIBE_CONSTLAT 0xF8  

Subscribe configuration for task CONSTLAT

  
SUBSCRIBE_LOWPWR 0xFC  

Subscribe configuration for task LOWPWR

  
EVENTS_POFWARN 0x108  

Power failure warning

  
EVENTS_SLEEPENTER 0x114  

CPU entered WFI/WFE sleep

  
EVENTS_SLEEPEXIT 0x118  

CPU exited WFI/WFE sleep

  
PUBLISH_POFWARN 0x188  

Publish configuration for event POFWARN

  
PUBLISH_SLEEPENTER 0x194  

Publish configuration for event SLEEPENTER

  
PUBLISH_SLEEPEXIT 0x198  

Publish configuration for event SLEEPEXIT

  
INTEN 0x300  

Enable or disable interrupt

  
INTENSET 0x304  

Enable interrupt

  
INTENCLR 0x308  

Disable interrupt

  
GPREGRET[n] 0x51C  

General purpose retention register

Retained
Parent topic: nRF5340 Product Specification

TASKS_CONSTLAT

Address offset: 0x78

Enable Constant Latency mode

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A W

TASKS_CONSTLAT

    

Enable Constant Latency mode

     

Trigger

1

Trigger task

Parent topic: nRF5340 Product Specification

TASKS_LOWPWR

Address offset: 0x7C

Enable Low-Power mode (variable latency)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A W

TASKS_LOWPWR

    

Enable Low-Power mode (variable latency)

     

Trigger

1

Trigger task

Parent topic: nRF5340 Product Specification

SUBSCRIBE_CONSTLAT

Address offset: 0xF8

Subscribe configuration for task CONSTLAT

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

CHIDX

  

[255..0]

DPPI channel that task CONSTLAT will subscribe to

B RW

EN

      

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

Parent topic: nRF5340 Product Specification

SUBSCRIBE_LOWPWR

Address offset: 0xFC

Subscribe configuration for task LOWPWR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

CHIDX

  

[255..0]

DPPI channel that task LOWPWR will subscribe to

B RW

EN

      

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

Parent topic: nRF5340 Product Specification

EVENTS_POFWARN

Address offset: 0x108

Power failure warning

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

EVENTS_POFWARN

    

Power failure warning

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

Parent topic: nRF5340 Product Specification

EVENTS_SLEEPENTER

Address offset: 0x114

CPU entered WFI/WFE sleep

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

EVENTS_SLEEPENTER

    

CPU entered WFI/WFE sleep

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

Parent topic: nRF5340 Product Specification

EVENTS_SLEEPEXIT

Address offset: 0x118

CPU exited WFI/WFE sleep

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

EVENTS_SLEEPEXIT

    

CPU exited WFI/WFE sleep

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

Parent topic: nRF5340 Product Specification

PUBLISH_POFWARN

Address offset: 0x188

Publish configuration for event POFWARN

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

CHIDX

  

[255..0]

DPPI channel that event POFWARN will publish to.

B RW

EN

      

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

Parent topic: nRF5340 Product Specification

PUBLISH_SLEEPENTER

Address offset: 0x194

Publish configuration for event SLEEPENTER

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

CHIDX

  

[255..0]

DPPI channel that event SLEEPENTER will publish to.

B RW

EN

      

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

Parent topic: nRF5340 Product Specification

PUBLISH_SLEEPEXIT

Address offset: 0x198

Publish configuration for event SLEEPEXIT

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

CHIDX

  

[255..0]

DPPI channel that event SLEEPEXIT will publish to.

B RW

EN

      

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

Parent topic: nRF5340 Product Specification

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                  

C

B

    

A

    
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

POFWARN

    

Enable or disable interrupt for event POFWARN

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

SLEEPENTER

    

Enable or disable interrupt for event SLEEPENTER

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

SLEEPEXIT

    

Enable or disable interrupt for event SLEEPEXIT

     

Disabled

0

Disable

     

Enabled

1

Enable

Parent topic: nRF5340 Product Specification

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                  

C

B

    

A

    
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

POFWARN

    

Write '1' to enable interrupt for event POFWARN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

SLEEPENTER

    

Write '1' to enable interrupt for event SLEEPENTER

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

    

Write '1' to enable interrupt for event SLEEPEXIT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Parent topic: nRF5340 Product Specification

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                  

C

B

    

A

    
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

POFWARN

    

Write '1' to disable interrupt for event POFWARN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

SLEEPENTER

    

Write '1' to disable interrupt for event SLEEPENTER

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

    

Write '1' to disable interrupt for event SLEEPEXIT

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Parent topic: nRF5340 Product Specification

GPREGRET[n] (n=0..1) (Retained)

Address offset: 0x51C + (n × 0x4)

This register is a retained register

General purpose retention register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

A

A

A

A

A

A

A

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

GPREGRET

    

General purpose retention register

This register is a retained register

Parent topic: nRF5340 Product Specification
This document was last updated on 2023-12-04.
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