Power and clock management

The power and clock management system in nRF5340 is optimized for ultra-low power applications to ensure maximum power efficiency.

The core of the power and clock management system is the power management unit (PMU) shown in the following figure.

Figure 1. Power management unit
Figure: Power management unit

The PMU automatically tracks the power and clock resources required by the different components in the system at any given time. To achieve the lowest power consumption possible, the PMU optimizes the system by evaluating power and clock requests, automatically starting and stopping clock sources, and choosing regulator operation modes.

The nRF5340 start-up sequence after reset is described in RESET — Reset control.

System ON mode

System ON is the default operation mode after power-on reset.

In System ON, all functional blocks, such as the CPU and peripherals, can be in an idle or run state depending on the configuration set by the software and the state of the executing application. The network core's CPU and peripherals can be in an idle state, run state, or Force-OFF mode (see Force-OFF mode).

The PMU can switch the appropriate internal power sources on and off, depending on how much power is needed. The power requirement of a peripheral is directly related to its activity level, which increases and decreases when specific tasks are triggered or events are generated.

Voltage and frequency scaling

nRF5340 automatically adjusts the internal voltages to optimize power efficiency, which is a trade off between performance and power consumption.

Some configuration options request a higher internal voltage, which is seen as an increase in power consumption. These configurations are the following:

  • Setting the frequency of the application core's clock to 128 MHz, see Application core frequency scaling. Increased power consumption in this mode is also observed when the CPU is sleeping, such as after executing the WFI (wait for interrupt) or WFE (wait for event) instructions.

    Power consumption during System ON idle sleep is reduced by configuring the application core's clock to 64 MHz before entering CPU sleep.

  • Using QSPI with 96 MHz clock frequency
  • Using the USB peripheral
  • When debugging
  • Requesting additional voltage on the VREGRADIO supply using VREQCTRL — Voltage request control

Power submodes

In System ON mode, when the CPU and all peripherals are IDLE, the system can reside in one of two power submodes.

The power submodes are:

  • Constant latency
  • Low-power

In Constant latency, the CPU wakeup latency and the PPI task response will be constant and kept at a minimum. This is secured by a set of resources that are always enabled. Compared to Low-power, the advantage of having a constant and predictable latency comes at a cost of increased power consumption. Constant latency is selected by triggering the CONSTLAT task.

In Low-power, the most power efficient supply option is chosen by the automatic power management system. Achieving the lowest power possible is at the expense of variations in CPU wakeup latency and PPI task response. Low-power is selected by triggering the LOWPWR task.

When the system enters System ON, it is by default in the Low-power submode.

System OFF mode

System OFF is the deepest power-saving mode the system can enter. In this mode, the system's core functionality is powered down and all ongoing tasks are terminated.

The device can be put into System OFF mode using the register SYSTEMOFF . The following initiate a wakeup from System OFF:

  • The DETECT signal, generated by the GPIO peripheral
  • The ANADETECT signal, generated by the LPCOMP peripheral
  • The SENSE signal, generated by the NFCT peripheral to wake-on-field
  • A valid USB voltage on the VBUS pin is detected
  • A debug session is started
  • A pin reset

When the device wakes up from System OFF, a system reset is performed. For more details, see Application core reset behavior.

One or more RAM sections can be retained in System OFF depending on the RAM retention settings in the peripheral VMC — Volatile memory controller.

Before entering System OFF, all on-going EasyDMA transactions should be completed. This is accomplished by making sure that the EasyDMA enabled peripheral is not active when entering System OFF. It is also recommended that the network core is in an idle state (i.e. peripherals are stopped and CPU is idle).

Emulated System OFF mode

When the device is in Debug Interface mode, System OFF is emulated to ensure that all resources required for debugging are available during System OFF.

Resources required for debugging include the following key components: Because the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF. This prevents the CPU from executing code that normally should not be executed. For more information, see Debug and trace.

Force-OFF mode

Force-OFF is only applicable for the network core.

The register interface RESET — Reset control is used by the application core to force the network core to Force-OFF mode. In this mode, the network core is stopped in order to achieve the lowest power consumption possible. When the network core is in Force-OFF mode, only the application core can release the mode, causing the network core to wake up and start the CPU again.

Before the application core sets the network core to Force-OFF mode, it is recommended that the network core is in an idle state, as defined by the following:
  • All peripherals are stopped.
  • Any additional voltage on the VREGRADIO supply is canceled using VREQCTRL — Voltage request control.
  • The CPU is an idle state, meaning it is running the WFI or WFE instruction.

When the network core wakes up from Force-OFF mode, it is reset. For more details, see Network core reset behavior.

Several RAM sections can be retained in Force-OFF mode depending on the RAM retention settings in the peripheral VMC — Volatile memory controller.

Emulated Force-OFF mode

If the device is in Debug Interface mode, Force-OFF mode will be emulated to secure the required resources needed for debugging.

When Force-OFF mode is emulated, the CPU and all peripherals are reset. The CPU is prevented from running during debug access to a core's resources, including writing to RAM, flash, and/or peripherals. See Debug and trace for more information.

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