Power and clock management
The power and clock management system in nRF5340 is optimized for ultra-low power applications to ensure maximum power efficiency.
The core of the power and clock management system is the power management unit (PMU) shown in the following figure.
The PMU automatically tracks the power and clock resources required by the different components in the system at any given time. To achieve the lowest power consumption possible, the PMU optimizes the system by evaluating power and clock requests, automatically starting and stopping clock sources, and choosing regulator operation modes.
The nRF5340 start-up sequence after reset is described in RESET — Reset control.
System ON mode
System ON is the default operation mode after power-on reset.
In System ON, all functional blocks, such as the CPU and peripherals, can be in an IDLE or RUN state depending on the configuration set by the software and the state of the executing application. The network core's CPU and peripherals can be in IDLE state, RUN state, or Force-OFF mode (see Force-OFF mode).
The PMU can switch the appropriate internal power sources on and off, depending on power requirements. A peripheral's power requirement is directly related to its activity level, which increases and decreases when specific tasks are triggered or events are generated.
Voltage and frequency scaling
nRF5340 automatically adjusts the internal voltages to optimize power efficiency.
Some configuration options request a higher internal voltage, which is seen as an increase in power consumption. These configurations are the following:
- Setting the frequency of the application core's clock to 128 MHz, see Application core frequency scaling. Increased power consumption in this mode is also observed when the CPU is sleeping, such as after executing the WFI (wait for interrupt) or WFE (wait for event) instructions.
Power consumption during System ON with CPU and peripherals in IDLE state sleep is reduced by configuring the application core's clock to 64 MHz before entering CPU sleep.
- Using QSPI with 96 MHz clock frequency
- Using the USB peripheral
- When debugging
- Requesting additional voltage on the VREGRADIO supply using VREQCTRL — Voltage request control
Power submodes
In System ON mode, when the CPU and all peripherals are in IDLE state, the system can reside in one of two power submodes.
The power submodes are:
- Constant latency
- Low-power
In Constant latency mode, the CPU wakeup latency and the PPI task response will be constant and kept at a minimum. This is secured by a set of resources that are always enabled. Compared to Low-power mode, the advantage of having a constant and predictable latency comes at a cost of increased power consumption. Constant latency mode is selected by triggering the CONSTLAT task.
In Low-power mode, the most power efficient supply option is chosen by the automatic power management system. Achieving the lowest power possible is at the expense of variations in CPU wakeup latency and PPI task response. Low-power mode is selected by triggering the LOWPWR task.
When the system enters System ON, it is by default in the Low-power submode.
System OFF mode
System OFF is the deepest power-saving mode the system can enter. In this mode, the system's core functionality is powered down and all ongoing tasks are terminated.
The device is put into System OFF mode using the register SYSTEMOFF . The following initiate a wakeup from System OFF:
- The DETECT signal, generated by the GPIO peripheral
- The ANADETECT signal, generated by the LPCOMP peripheral
- The SENSE signal, generated by the NFCT peripheral to wake-on-field
- A valid USB voltage on the VBUS pin is detected
- A debug session is started
- A pin reset
When the device wakes up from System OFF, a system reset is performed. For more details, see Application core reset behavior.
One or more RAM sections can be retained in System OFF depending on the RAM retention settings in the peripheral VMC — Volatile memory controller.
Before entering System OFF, the EasyDMA enabled peripheral must not active when entering System OFF. It is also recommended that the network core is in IDLE state, meaning peripherals are stopped and the CPU is idle.
Emulated System OFF mode
When the device is in Debug Interface mode, System OFF is emulated to ensure that all resources required for debugging are available during System OFF.
- Debug Interface mode
- CLOCK — Clock control
- POWER — Power control
- OSCILLATORS — Oscillator control
- REGULATORS — Regulator control
- RESET — Reset control
- NVMC — Non-volatile memory controller
- CPU
- Flash memory
- RAM
Force-OFF mode
Force-OFF mode is only applicable for the network core.
The register interface RESET — Reset control is used by the application core to force the network core to Force-OFF mode. In this mode, the network core is stopped in order to achieve the lowest power consumption possible. When the network core is in Force-OFF mode, only the application core can release the mode, causing the network core to wake up and start the CPU again.
- All peripherals are stopped
- Additional voltage on the VREGRADIO supply is canceled using VREQCTRL — Voltage request control
- The CPU is in IDLE state, meaning it is running the WFI or WFE instruction
When the network core wakes up from Force-OFF mode, it is reset. For more details, see Network core reset behavior.
Several RAM sections can be retained in Force-OFF mode depending on the RAM retention settings in the peripheral VMC — Volatile memory controller.
Emulated Force-OFF mode
If the device is in Debug Interface mode, Force-OFF mode will be emulated to secure the required resources needed for debugging.
When Force-OFF mode is emulated, the CPU and all peripherals are reset. The CPU is prevented from running during debug access to a core's resources, including writing to RAM, flash, and/or peripherals. See Debug and trace for more information.