RESET - Reset control

A reset in the system is triggered by either a system-level or core-level reset source.

A system-level reset will reset all cores. Power-on reset, brownout reset, and pin reset are examples of a system-level reset. A core-level reset, such as a soft reset or a lockup, will reset either the entire core or only part of it. The different reset sources in the system are illustrated in the following figure.

Figure 1. Reset sources
Reset resources

After a system-level reset, the application core will start up on its own and will then start the network core as necessary.

After a reset has occurred, the register RESETREAS can be read to determine which source generated the reset. Each core has its own RESETREAS register. System-level and application core reset sources are also available in the network core's RESETREAS register, unless otherwise noted.

Power-on reset

The power-on reset (POR) generator initializes the system when the VDD supply voltage is above the power-on threshold. This also applies in high voltage mode, where the VDD supply voltage is provided by the high voltage regulator (VREGH).

The system is held in a reset state until the supply has reached the minimum operating voltage, and the internal voltage regulators have started. After a power-on reset, the application core is started while the network core is held in reset, see Network force off.

Pin reset

A pin reset is generated when the physical reset pin on the device is asserted.

Similar to a power-on reset, the application core is started after the reset pin is deasserted. The network core is held in reset, see Network force off.

The reset pin has an internal pull-up resistor with the same resistance as GPIO pull-ups, see GPIO — General purpose input/output.

Brownout reset

The brownout reset (BOR) generator puts the system in reset state if the VDD supply voltage drops below the brownout reset threshold. This also applies in high voltage mode, where the VDD supply voltage is provided by the high voltage regulator (VREGH).

Similar to a power-on reset, the application core is started after BOR is deasserted while the network core is held in reset, see Network force off.

Wakeup from System OFF mode reset

The device is reset when it wakes up from System OFF mode.

Similar to a power-on reset, the application core is started while the network core is held in reset, see Network force off.

If the device is in debug interface mode, the debug acces port (DAP) is not reset after a wakeup from System OFF. For more information, see Overview.

Soft reset

Soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR) in the Arm® core of the application and network cores is set. For more information, see ARM documentation.

When the application core performs a soft reset, the network core is held in reset, see Network force off. A soft reset in the network core will only cause the network core to reset.

A soft reset can also be generated using the RESET register in the associated CTRL-AP.

Watchdog timer reset

A watchdog timer (WDT) reset is generated when the watchdog timer times out.

Each core has its own WDT instance. When the application core gets a WDT reset, the network core is held in reset, see Network force off. A WDT reset in the network core will only cause the network core to reset. The reset target depends on the core where WDT is instantiated.

Note: Because the network core WDT reset is local for the network core, the application core is not aware of WDT timing out in the network core. Notifying the application core is possible. One way is to check the register RESETREAS for WDT flags and report the error through inter-processor communication (IPC).

For more information about WDT, see WDT — Watchdog timer. More information about IPC is available in IPC — Interprocessor communication.

Network force off

The application core can force off the network core, which resets it and switches off its power and clocks.

A FORCEOFF can be issued to the network core by the application core. To force off the network core, use the register NETWORK.FORCEOFF.

Application core resets implicitly result in a force off of the network core. The network core will be held in force off until the application core releases the force off signal from the NETWORK.FORCEOFF register.

Retained registers

A retained register is one that retains its value in System OFF and/or Force off mode and when reset, depending on the reset source. See individual peripheral chapters for information about which registers are retained for the various peripherals.

Application core reset behavior

Application core reset behavior depends on the reset source.

Any reset in the application core will cause a network core force off, triggering the FORCEOFF reset source in the network core. For more information, see Network force off.

In System OFF mode, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

If the device is in Debug Interface mode, the debug components will not be reset. Additionally, CPU lockup will not generate a reset. See Overview for more information about the different debug components in the system.

Application core reset targets and their reset sources are summarized in the following table.

Table 1. Application core reset targets and their reset sources. An 'x' in the table means that the specific module is reset.
Reset source Reset target
CPU Network core Debug RAM WDT RESETREAS
CPU lockup x x        
Soft reset x x        
Wakeup from System OFF mode reset x x x x1 x  
Watchdog timer reset x x x x x  
Pin reset x x x x x  
Brownout reset x x x x x x
Power-on reset x x x x x x
NETWORK.FORCEOFF   x        

Note: RAM is never reset, but depending on the reset source, its content may be corrupted.

Some retained registers may have a different reset behavior, as shown in the following table.

Table 2. Application core reset behavior for retained registers. An 'x' in the table means that the specific module is reset.
Reset source Reset target
Regular peripheral registers SPU GPIO REGULATORS, OSCILLATORS POWER.GPREGRET
CPU lockup x x x    
Soft reset x x x    
Wakeup from System OFF mode reset x        
Watchdog timer reset x x x x  
Pin reset x x x x  
Brownout reset x x x x x
Power-on reset x x x x x

Network core reset behavior

Network core reset behavior depends on the reset source.

In System OFF mode, or when the network core is held in force-off, the watchdog timer is not running and there is no CPU lockup possible. RAM may be fully or partially retained, depending on RAM retention settings in VMC — Volatile memory controller.

If the device is in Debug Interface mode, the debug components will not be reset. Additionally, CPU lockup will not generate a reset. See Overview for more information about the different debug components in the system.

Any reset in the application core will cause a network core force off, triggering the network FORCEOFF reset source in the following table. For more information, see Network force off.

Table 3. Network core reset target sources. An 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source Reset target
CPU RAM WDT RESETREAS
CPU lockup x      
Soft reset x      
Network FORCEOFF x x2 x  
Application Watchdog timer reset x x x  
Local Watchdog timer reset x x x  

Note: RAM is never reset, but its content may be corrupted depending on the reset source.

Some retained registers may have a different reset behavior, as shown in following table.

Table 4. Network core reset behavior for retained registers. An 'x' in the table means that the specific module is reset. Pin reset, brownout reset, and power-on reset are system level reset sources with the network core and application core having the same behavior, see Application core reset behavior.
Reset source Reset target
Regular peripheral registers GPIO POWER.GPREGRET
CPU lockup x x 3  
Soft reset x x 3  
Network FORCEOFF x    
Application Watchdog timer reset x x  
Local Watchdog timer reset x x  

Registers

Table 5. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50005000
0x40005000

APPLICATION RESET

RESET : S
RESET : NS

US

NA

Reset control and status

   
0x41005000 NETWORK RESET RESET NS NA

Reset status

   
Table 6. Register overview
Register Offset Security Description
RESETREAS 0x400  

Reset reason

 
NETWORK.FORCEOFF 0x614  

Force off power and clock in network core

 

RESETREAS

Address offset: 0x400

Reset reason

Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID        

Q

P O N M       K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

RESETPIN

   

Reset from pin reset detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

B RW

DOG0

   

Reset from application watchdog timer 0 detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

C RW

CTRLAP

   

Reset from application CTRL-AP detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

D RW

SREQ

   

Reset from application soft reset detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

E RW

LOCKUP

   

Reset from application CPU lockup detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

F RW

OFF

   

Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO

     

NotDetected

0

Not detected

     

Detected

1

Detected

G RW

LPCOMP

   

Reset due to wakeup from System OFF mode when wakeup is triggered by ANADETECT signal from LPCOMP

     

NotDetected

0

Not detected

     

Detected

1

Detected

H RW

DIF

   

Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode

     

NotDetected

0

Not detected

     

Detected

1

Detected

I RW

LSREQ

   

Reset from network soft reset detected

Note: Not available for application core

     

NotDetected

0

Not detected

     

Detected

1

Detected

J RW

LLOCKUP

   

Reset from network CPU lockup detected

Note: Not available for application core

     

NotDetected

0

Not detected

     

Detected

1

Detected

K RW

LDOG

   

Reset from network watchdog timer detected

Note: Not available for application core

     

NotDetected

0

Not detected

     

Detected

1

Detected

M RW

MFORCEOFF

   

Force off reset from application core detected

Note: Not available for application core

     

NotDetected

0

Not detected

     

Detected

1

Detected

N RW

NFC

   

Reset after wakeup from System OFF mode due to NFC field being detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

O RW

DOG1

   

Reset from application watchdog timer 1 detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

P RW

VBUS

   

Reset after wakeup from System OFF mode due to VBUS rising into valid range

     

NotDetected

0

Not detected

     

Detected

1

Detected

Q RW

LCTRLAP

   

Reset from network CTRL-AP detected

Note: Not available for application core

     

NotDetected

0

Not detected

     

Detected

1

Detected

NETWORK.FORCEOFF

Address offset: 0x614

Force off power and clock in network core

Not available for network core

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A RW

FORCEOFF

   

Force off power and clock in network core

     

Release

0

Release force off signal

     

Hold

1

Hold force off signal

1 Depending on RAM retention settings.
2 Depending on RAM retention settings.
3 MCUSEL settings are kept.

This document was last updated on
2019-12-09.
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