CTRL-AP - Control access port

The control access port (CTRL-AP) is a custom access port that enables control of the device when other debug access ports (DAP) have been disabled by the access port protection.

For an overview of the other debug access ports, see DAP — Debug access port.
Figure 1. Control access port details
Control access port details

Access port protection (APPROTECT) blocks the debugger access to the AHB-AP, and prevents read and write access to all CPU registers and memory-mapped addresses. To enable port protection access for both secure and non-secure modes, use the registers UICR.SECUREAPPROTECT and UICR.APPROTECT , as well as CTRLAP.APPROTECT.DISABLE and CTRLAP.SECUREAPPROTECT.DISABLE. The debugger can use the register to read the status of secure and non-secure access port protection.

Erase protection (ERASEPROTECT) protects the flash and UICR parts of the non-volatile memory from being erased. Erase protection can be temporarily disabled from the control access port.

CTRL-AP has the following features:
  • Soft reset
  • Erase all
  • Mailbox interface
  • Debug of protected devices

Reset request

The debugger can request the device to perform a soft reset.

Use the register RESET to request a soft reset. Once the soft reset is performed, the reset reason is accessible on the on-chip firmware through the RESETREAS register. For more information about the soft reset, see RESET — Reset control.

Erase all

The erase all function lets the debugger trigger an erase of flash, user information configuration registers (UICR), RAM, all peripheral settings, and also temporarily removes the access port protection.

To trigger an erase all function, the debugger writes to the register ERASEALL. The register ERASEALLSTATUS will read as busy for the duration of the operation. The ERASEALL mechanism completes its tasks by writing UICR.APPROTECT to the Unprotected value, in addition to writing the CPU side CTRLAP.SECUREAPPROTECT.DISABLE and CTRLAP.APPROTECT.DISABLE registers to the value 0x50FA50FA. After the next soft reset, the access port protection is temporarily removed. This temporary unprotection is removed by the next pin reset, power-on reset, brown-out reset, or watchdog timer reset. For more information about access port protection, see Access port protection.

If the debugger performs an erase all function on a slave MCU, the erase sequence will always erase the application MCU first, independently of how the application is protected, before erasing the slave MCU.

Erase all protection

It is possible to prevent the debugger from performing an erase all operation by writing to the UICR.ERASEPROTECT register. Once the register is configured and the device is reset, the CTRL-AP ERASEALL operation is disabled, and all flash write and erase operations are restricted to the firmware. In addition, it is still possible to write/erase from the debugger as long as the UICR.APPROTECT register is not set.

Note: Setting the UICR.ERASEPROTECT register only affects the erase all operation and not the debugger access.

The register ERASEPROTECT.STATUS holds the status for erase protection.

Mailbox interface

CTRL-AP implements a mailbox interface which enables the CPU to communicate with a debugger over the SWD interface.

The mailbox interface consists of a transmit register MAILBOX.TXDATA with its corresponding status register MAILBOX.TXSTATUS, and a receive register MAILBOX.RXDATA with its corresponding status register MAILBOX.RXSTATUS. Status bits in the TXSTATUS/RXSTATUS registers are set and cleared automatically when the TXDATA/RXDATA registers are written to and read from, independently of the direction.
Figure 2. Mailbox register interface
Mailbox register interface, illustrating the data flow between debugger and CPU

Mailbox transfer sequence

  1. Sender writes TXDATA.
  2. Hardware sets sender's TXSTATUS to DataPending.
  3. Hardware sets receiver's RXSTATUS to DataPending.
  4. Receiver reads RXDATA.
  5. Hardware sets receiver's RXSTATUS to NoDataPending.
  6. Hardware sets sender's TXSTATUS to NoDataPending.

Disabling erase protection

The erase protection mechanism can be disabled to return a device to factory default settings on next reset.

The debugger can read the erase protection status in the register ERASEPROTECT.STATUS.

If ERASEPROTECT has been enabled, both the debugger and on-chip firmware must write the same non-zero 32-bit KEY value into their respective ERASEPROTECT.DISABLE registers to disable the erase protection. When both registers have been written with the same non-zero 32-bit KEY value, the device is automatically erased as described in Erase all. The access ports will be re-enabled on the next reset once the secure erase sequence has completed.

The write-once register ERASEPROTECT.LOCK should be set to Locked as early as possible in the start-up sequence, preferably as soon as the on-chip firmware has determined it does not need to communicate with a debugger over the CTRL-AP mailbox interface. Once written, it will not be possible to remove the erase protection until the next reset.

Disabling access port protection

The access port protection mechanisms can be temporarily disabled to debug the device.

The disabling of the access port protection is done through a combination of UICR and CTRL-AP registers.

Disabling non-secure access port protection

If UICR.APPROTECT has been enabled from UICR, the device access port is protected.

If UICR.APPROTECT has not been enabled from UICR, both the debugger and on-chip firmware must write the same non-zero 32-bit KEY value into their respective registers CTRLAP.APPROTECT.DISABLE (CPU-side) and CTRLAP.APPROTECT.DISABLE (debugger-side) to disable the access port protection to non-secure mode.

The write-once register APPROTECT.LOCK should be set to Locked as early as possible in the start-up sequence. Once written, it will not be possible to remove the non-secure mode access port protection until next reset.

Disabling secure access port protection

If UICR.APPROTECT has been enabled from UICR, the device access port is protected.

If UICR.SECUREAPPROTECT has not been enabled from UICR, both the debugger and on-chip firmware must write the same non-zero 32-bit KEY value into their respective registers CTRLAP.SECUREAPPROTECT.DISABLE (CPU-side) and CTRLAP.SECUREAPPROTECT.DISABLE (debugger-side) to disable the access port protection to secure mode.

The write-once register SECUREAPPROTECT.LOCK should be set to Locked as early as possible in the start-up sequence, preferably as soon as on-chip firmware has determined it does not need to communicate with a debugger over the CTRL-AP mailbox interface. Once written, it will not be possible to remove the secure mode access port protection until next reset.

Note: If secure mode debug is enabled, an ERASEALL sequence can also be initiated by writing the same 32-bit KEY value into the respective ERASEPROTECT.DISABLE registers

The CTRLAP.APPROTECT.DISABLE and CTRLAP.SECUREAPPROTECT.DISABLE registers are only reset by pin reset, brown-out reset, or watchdog timer reset. This allows keeping the debug session active through soft resets.

After an ERASEALL sequence has completed, the access port protection of the core's AHB-AP is disabled until the next pin reset, power-on reset, brown-out reset, or watchdog timer reset. This will allow initial firmware to be written. For more details on ERASEALL, see Erase all.

Access port protection status

The debugger can read the access port protection status in the core's AHB-AP, using the Arm® AHB-AP Control/Status Word register (CSW), defined in the Arm CoreSight™ SoC-400 Technical Reference Manual, Revision r3p2. The DbgStatus field indicates that the AHB-AP can perform AHB transfers, while the SPIStatus indicates if secure AHB transfers are permitted. For a list of all debug access ports, see DAP — Debug access port.

Debugger registers

CTRL-AP has a set of registers that can only be accessed from the debugger over the SWD interface. These are not accessible from the CPU.

The SECUREAPPROTECT fields and registers only apply for cores that have the Arm Cortex-M33 with TrustZone technology.

Registers

Table 1. Register overview
Register Offset Security Description
RESET 0x000  

System reset request.

 
ERASEALL 0x004  

Perform a secure erase of the device, where flash, SRAM, and UICR will be erased in sequence. The device will be returned to factory default settings upon next reset.

 
ERASEALLSTATUS 0x008  

This is the status register for the ERASEALL operation.

 
APPROTECT.DISABLE 0x010  

This register disables APPROTECT and enables debug access to non-secure mode.

 
SECUREAPPROTECT.DISABLE 0x014  

This register disables SECUREAPPROTECT and enables debug access to secure mode.

 
ERASEPROTECT.STATUS 0x018  

This is the status register for the UICR ERASEPROTECT configuration.

 
ERASEPROTECT.DISABLE 0x01C  

This register disables ERASEPROTECT and performs ERASEALL.

 
MAILBOX.TXDATA 0x020  

Data sent from the debugger to the CPU.

 
MAILBOX.TXSTATUS 0x024  

This register shows a status that indicates if data sent from the debugger to the CPU has been read.

 
MAILBOX.RXDATA 0x028  

Data sent from the CPU to the debugger.

 
MAILBOX.RXSTATUS 0x02C  

This register shows a status that indicates if data sent from the CPU to the debugger has been read.

 
IDR 0x0FC  

CTRL-AP Identification Register, IDR.

 

RESET

Address offset: 0x000

System reset request.

This register is automatically deactivated during an ERASEALL operation.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

RESET

   

System reset request and status

     

NoReset

0

Write to release reset

Reading '0' means reset is not active

     

Reset

1

Write to hold reset

Reading '1' means reset is active

ERASEALL

Address offset: 0x004

Perform a secure erase of the device, where flash, SRAM, and UICR will be erased in sequence. The device will be returned to factory default settings upon next reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A W

ERASEALL

   

Return device to factory default settings

     

NoOperation

0

No operation

     

Erase

1

Erase flash, SRAM, and UICR in sequence

ERASEALLSTATUS

Address offset: 0x008

This is the status register for the ERASEALL operation.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

ERASEALLSTATUS

   

Status bit for the ERASEALL operation

     

Ready

0

ERASEALL is ready

     

Busy

1

ERASEALL is busy (on-going)

APPROTECT.DISABLE

Address offset: 0x010

This register disables APPROTECT and enables debug access to non-secure mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x50FA50FA 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0
ID R/W Field Value ID Value Description
A RW

KEY

   

Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if KEY fields match.

The current APPROTECT value as configured from CTRL-AP is disabled if the value of KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.

To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled.

SECUREAPPROTECT.DISABLE

Address offset: 0x014

This register disables SECUREAPPROTECT and enables debug access to secure mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x50FA50FA 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 1 0 1 0
ID R/W Field Value ID Value Description
A RW

KEY

   

Disable SECUREAPPROTECT and enable debug of secure mode until the next pin reset if KEY fields match.

The current SECUREAPPROTECT value as configured from CTRL-AP is disabled if the value of KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.

To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled.

ERASEPROTECT.STATUS

Address offset: 0x018

This is the status register for the UICR ERASEPROTECT configuration.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

PALL

   

Status bit for erase protection

Note: The reset value is auto read from the ERASEPROTECT register in UICR.

     

Enabled

0

ERASEPROTECT is enabled

     

Disabled

1

ERASEPROTECT is not enabled and ERASEALL can be performed

ERASEPROTECT.DISABLE

Address offset: 0x01C

This register disables ERASEPROTECT and performs ERASEALL.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

KEY

   

The ERASEALL sequence will be initiated if value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.

MAILBOX.TXDATA

Address offset: 0x020

Data sent from the debugger to the CPU.

Writing to this register will automatically set a DataPending value in the TXSTATUS register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

Data

   

Data sent from debugger

MAILBOX.TXSTATUS

Address offset: 0x024

This register shows a status that indicates if data sent from the debugger to the CPU has been read.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

Status

   

Status of register DATA

     

NoDataPending

0

No data pending in register TXDATA

     

DataPending

1

Data pending in register TXDATA

MAILBOX.RXDATA

Address offset: 0x028

Data sent from the CPU to the debugger.

Reading from this register will automatically set a NoDataPending value in the RXSTATUS register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

Data

   

Data sent from CPU

MAILBOX.RXSTATUS

Address offset: 0x02C

This register shows a status that indicates if data sent from the CPU to the debugger has been read.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

Status

   

Status of register DATA

     

NoDataPending

0

No data pending in register RXDATA

     

DataPending

1

Data pending in register RXDATA

IDR

Address offset: 0x0FC

CTRL-AP Identification Register, IDR.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E E E E D D D D C C C C C C C B B B B           A A A A A A A A
Reset 0x12880000 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

APID

   

AP Identification

B R

CLASS

   

Access Port (AP) class

     

NotDefined

0x0

No defined class

     

MEMAP

0x8

Memory Access Port

C R

JEP106ID

   

JEDEC JEP106 identity code

D R

JEP106CONT

   

JEDEC JEP106 continuation code

E R

REVISION

   

Revision

Registers

Table 2. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50006000
0x40006000

APPLICATION CTRLAPPERI

CTRLAP : S
CTRLAP : NS

US

NSA

Control access port CPU side

   
0x41006000 NETWORK CTRLAPPERI CTRLAP NS NA

Control access port CPU side

SECUREAPPROTECT.LOCK, SECUREAPPROTECT.DISABLE, and STATUS.SECUREAPPROTECT registers not supported.

 
Table 3. Register overview
Register Offset Security Description
MAILBOX.RXDATA 0x400  

Data sent from the debugger to the CPU.

 
MAILBOX.RXSTATUS 0x404  

This register shows a status that indicates if data sent from the debugger to the CPU has been read.

 
MAILBOX.TXDATA 0x480  

Data sent from the CPU to the debugger.

 
MAILBOX.TXSTATUS 0x484  

This register shows a status that indicates if the data sent from the CPU to the debugger has been read.

 
ERASEPROTECT.LOCK 0x500  

This register locks the ERASEPROTECT.DISABLE register from being written until next reset.

 
ERASEPROTECT.DISABLE 0x504  

This register disables the ERASEPROTECT register and performs an ERASEALL operation.

 
APPROTECT.LOCK 0x540  

This register locks the APPROTECT.DISABLE register from being written to until next reset.

 
APPROTECT.DISABLE 0x544  

This register disables the APPROTECT register and enables debug access to non-secure mode.

 
SECUREAPPROTECT.LOCK 0x548  

This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset.

 
SECUREAPPROTECT.DISABLE 0x54C  

This register disables the SECUREAPPROTECT register and enables debug access to secure mode.

 
STATUS 0x600  

Status bits for CTRL-AP peripheral.

 

MAILBOX.RXDATA

Address offset: 0x400

Data sent from the debugger to the CPU.

Reading from this register will automatically set a NoDataPending value in the RXSTATUS register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

RXDATA

   

Data received from debugger

MAILBOX.RXSTATUS

Address offset: 0x404

This register shows a status that indicates if data sent from the debugger to the CPU has been read.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

RXSTATUS

   

Status of data in register RXDATA

     

NoDataPending

0

No data pending in register RXDATA

     

DataPending

1

Data pending in register RXDATA

MAILBOX.TXDATA

Address offset: 0x480

Data sent from the CPU to the debugger.

Writing to this register will automatically set a DataPending value in the TXSTATUS register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

TXDATA

   

Data sent to debugger

MAILBOX.TXSTATUS

Address offset: 0x484

This register shows a status that indicates if the data sent from the CPU to the debugger has been read.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

TXSTATUS

   

Status of data in register TXDATA

     

NoDataPending

0

No data pending in register TXDATA

     

DataPending

1

Data pending in register TXDATA

ERASEPROTECT.LOCK

Address offset: 0x500

This register locks the ERASEPROTECT.DISABLE register from being written until next reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW1

LOCK

   

Lock ERASEPROTECT.DISABLE register from being written until next reset

     

Unlocked

0

Register ERASEPROTECT.DISABLE is writeable

     

Locked

1

Register ERASEPROTECT.DISABLE is read-only

ERASEPROTECT.DISABLE

Address offset: 0x504

This register disables the ERASEPROTECT register and performs an ERASEALL operation.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW1

KEY

   

The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides.

APPROTECT.LOCK

Address offset: 0x540

This register locks the APPROTECT.DISABLE register from being written to until next reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW1

LOCK

   

Lock the APPROTECT.DISABLE register from being written to until next reset

     

Unlocked

0

Register APPROTECT.DISABLE is writeable

     

Locked

1

Register APPROTECT.DISABLE is read-only

APPROTECT.DISABLE

Address offset: 0x544

This register disables the APPROTECT register and enables debug access to non-secure mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

KEY

   

If the value of the KEY field is non-zero, and the KEY fields match on both the CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until the next pin reset, brown-out reset, power-on reset, or watchog timer reset.

After reset the debugger side register has a fixed KEY value.

To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled.

SECUREAPPROTECT.LOCK

Address offset: 0x548

This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW1

LOCK

   

Lock register SECUREAPPROTECT.DISABLE from being written until next reset

     

Unlocked

0

Register SECUREAPPROTECT.DISABLE is writeable

     

Locked

1

Register SECUREAPPROTECT.DISABLE is read-only

SECUREAPPROTECT.DISABLE

Address offset: 0x54C

This register disables the SECUREAPPROTECT register and enables debug access to secure mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A RW

KEY

   

If the value of the KEY field is non-zero, and the KEY fields match on both the CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until the next pin reset, brown-out reset, power-on reset, or watchog timer reset.

After reset the debugger side register has a fixed KEY value.

To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled.

STATUS

Address offset: 0x600

Status bits for CTRL-AP peripheral.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                          

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A R

UICRAPPROTECT

   

Status bit for UICR part of access port protection at last reset.

The reset value is automatically read from the APPROTECT register in UICR.

     

Enabled

0

APPROTECT was enabled in UICR

     

Disabled

1

APPROTECT wasdisabled in UICR

B R

UICRSECUREAPPROTECT

   

Status bit for UICR part of secure access port protection at last reset.

The reset value is automatically read from the SECUREAPPROTECT register in UICR.

     

Enabled

0

SECUREAPPROTECT was enabled in UICR

     

Disabled

1

SECUREAPPROTECT was disabled in UICR

C R

DBGIFACEMODE

   

Status bit for device debug interface mode

     

Disabled

0

No debugger attached

     

Enabled

1

Debugger is attached and device is in debug interface mode


This document was last updated on
2021-09-27.
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