SAADC — Successive approximation analog-to-digital converter

The ADC can coexist with COMP and other peripherals using one of AIN0-AIN7, provided these are assigned to different pins.

It is not recommended to select the same analog input pin for both modules.

The ADC supports up to eight external analog input channels. It can be operated in One-shot mode with sampling under software control, or Continuous mode with a programmable sampling rate.

Figure 1. Simplified ADC block diagram

Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with single-ended input SE in the MODE field of the CH[n].CONFIG register. In Single-ended (SE) mode, the negative input will be shorted to ground internally.

In Single-ended mode, the assumption is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB. This can be reduced by configuring SAADC to use differential measurent setting the MODE field of the CH[n].CONFIG register to Diff (differential).

The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as shown in the following equation.

RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION - m)

The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors due to high source impedance and sampling jitter. For battery measurement, the DC errors are most noticeable.

The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential, and the input must be scaled accordingly.

The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, it is recommended to run CALIBRATEOFFSET at regular intervals. The CALIBRATEDONE, DONE, and RESULTDONE events will be generated when the calibration has completed.

Up to eight analog input channels, CH[n](n=0..7), can be configured.

See Shared resources for shared input with comparators.

Any of the available channels can be enabled for the ADC to operate in One-shot mode. If more than one CH[n] is configured, the ADC enters Scan mode.

An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also enables the particular channel.

An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register will have no effect unless Differential mode is enabled, see MODE field in the CH[n].CONFIG register.

If more than one of the CH[n].PSELP registers is set, the device enters Scan mode. Input selections in Scan mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if the particular scan channel is specified as differential, see MODE field in the CH[n].CONFIG register.

The ADC input configuration supports One-shot mode, Continuous mode, and Scan mode.

The ADC indicates a single ongoing conversion via the register STATUS. During Scan mode, oversampling, or Continuous modes, more than a single conversion take place in the ADC. As a consequence, the value reflected in the STATUS register will toggle at the end of each single conversion.

After configuring RESULT.PTR and RESULT.MAXCNT, the ADC resources are started by triggering the START task. The ADC is using EasyDMA to store results in a Result buffer in RAM.

The Result buffer is located at the address specified in the RESULT.PTR register. The RESULT.PTR register is double-buffered and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the Result buffer is specified in the RESULT.MAXCNT register and the ADC will generate an END event when it has filled up the Result buffer, see ADC. Results are stored in little-endian byte order in Data RAM. Every sample will be sign extended to 16 bit before stored in the Result buffer.

The ADC is stopped by triggering the STOP task. The STOP task will terminate an ongoing sampling. The ADC will generate a STOPPED event when it has stopped. If the ADC is already stopped when the STOP task is triggered, the STOPPED event will still be generated.

Figure 4. ADC

If the RESULT.PTR is not pointing to a RAM region accessible from the peripheral, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory for more information about the different memory regions.

The EasyDMA will have finished accessing the RAM when the END or STOPPED event has been generated.

The RESULT.AMOUNT register can be read following an END event or a STOPPED event to see how many results have been transferred to the Result buffer in RAM since the START task was triggered.

In Scan mode, SAMPLE tasks can be triggered once the START task is triggered. The END event is generated when the number of samples transferred to memory reaches the value specified by RESULT.MAXCNT. After an END event, the START task needs to be triggered again before new samples can be taken. By specifying RESULT.MAXCNT ≥ number of channels enabled, the size of the Result buffer should be large enough for a minimum of one result from each of the enabled channels. See Scan mode for more information.

The ADC has an internal resistor string for positive and negative input.

The resistors in the following figure are controlled in the CH[n].CONFIG.RESP and CH[n].CONFIG.RESN registers.

Figure 5. Resistor ladder for positive input

The ADC can use the following two references, controlled in the REFSEL field of the CH[n].CONFIG register.

• Internal reference
• VDD as reference

The internal reference results in an input range of ±0.6 V on the ADC core. VDD as reference results in an input range of ±VDD/4 on the ADC core. The gain block can be used to change the effective input range of the ADC.

Input range = (+- 0.6 V or +-VDD/4)/Gain

For example, choosing VDD as reference, single ended input (grounded negative input), and a gain of 1/4 the input range is the following:

Input range = (VDD/4)/(1/4) = VDD

With internal reference, single ended input (grounded negative input), and a gain of 1/6 the input range is the following:

Input range = (0.6 V)/(1/6) = 3.6 V

The AIN0 - AIN7 inputs cannot exceed VDD, or be lower than VSS.

To sample the input voltage, the ADC connects a capacitor to the input.

The acquisition time indicates how long the capacitor is connected, see TACQ field in register CH[n].CONFIG (n=0..7). The required acquisition time depends on the source (R_source) resistance. For high source resistance, the acquisition time should be increased. See the following table for more information.

Figure 6. Simplified ADC sample network

When using VDDHDIV5 as input, the acquisition time needs to be 10 µs or higher.

A channel can be event monitored by configuring limit register CH[n].LIMIT.

If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will get fired.

Figure 7. Example of limits monitoring on channel 'n'

The CH[n].LIMIT.HIGH shall always be higher than or equal to CH[n].LIMIT.LOW . In other words, an event can be generated only when the input signal has been sampled outside of the defined limits. It is not possible to generate an event when the input signal is inside a defined range by swapping high and low limits.

The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a channel, the software shall simply ignore the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.