Memory

The application core contains flash memory and RAM that can be used for code and data storage.

The following figure shows how the CPU, network core, and peripherals with EasyDMA can access RAM via the AHB multilayer interconnect. The domain configuration (DCNF) registers can block access from external DMA masters, see DCNF — Domain configuration.

Figure 1. Memory layout

Peripheral instantiation

The following table describes the abbreviations used in the Instance, Secure mapping, and DMA security columns of the instantiation table.

Table 1. Instantiation table abbreviations
Abbreviation	Description
NS	Non-secure - Peripheral is always accessible as a Non-Secure peripheral
S	Secure - Peripheral is always accessible as a Secure peripheral
US	User Selectable - A Secure or Non-secure attribute for the peripheral is defined in the SPU
SPLIT	Both Secure and Non-secure - The same resource is shared by both secure and non-secure code
NA	Not Applicable - Peripheral has no DMA capability
NSA	NoSeparateAttribute - Peripheral with DMA and DMA transfer has the same security attribute as assigned to the peripheral
SA	SeparateAttribute - Peripheral with DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral

The Secure mapping column in the following table defines configuration capabilities for the Arm® TrustZone® for Armv8-M secure attribute. The DMA security column describes the DMA capabilities of the peripheral.

Instantiation

Table 2. Instantiation table
ID	Base address	Peripheral	Instance	Secure mapping	DMA security	Description
0	0x50000000 0x40000000	DCNF	DCNF : S DCNF : NS	US	NA	Domain configuration
0	0x50000000 0x40000000	FPU	FPU : S FPU : NS	US	NA	Floating Point unit interrupt control
1	0x50001000	CACHE	CACHE	S	NA	Cache
3	0x50003000	SPU	SPU	S	NA	System protection unit
4	0x50004000 0x40004000	OSCILLATORS	OSCILLATORS : S OSCILLATORS : NS	US	NA	Oscillator configuration
4	0x50004000 0x40004000	REGULATORS	REGULATORS : S REGULATORS : NS	US	NA	Regulator configuration
5	0x50005000 0x40005000	CLOCK	CLOCK : S CLOCK : NS	US	NA	Clock control
5	0x50005000 0x40005000	POWER	POWER : S POWER : NS	US	NA	Power control
5	0x50005000 0x40005000	RESET	RESET : S RESET : NS	US	NA	Reset control and status
6	0x50006000 0x40006000	CTRLAPPERI	CTRLAP : S CTRLAP : NS	US	NSA	Control access port CPU side
8	0x50008000 0x40008000	SPIM	SPIM0 : S SPIM0 : NS	US	SA	SPI master 0
8	0x50008000 0x40008000	SPIS	SPIS0 : S SPIS0 : NS	US	SA	SPI slave 0
8	0x50008000 0x40008000	TWIM	TWIM0 : S TWIM0 : NS	US	SA	Two-wire interface master 0
8	0x50008000 0x40008000	TWIS	TWIS0 : S TWIS0 : NS	US	SA	Two-wire interface slave 0
8	0x50008000 0x40008000	UARTE	UARTE0 : S UARTE0 : NS	US	SA	Universal asynchronous receiver/transmitter with EasyDMA 0
9	0x50009000 0x40009000	SPIM	SPIM1 : S SPIM1 : NS	US	SA	SPI master 1
9	0x50009000 0x40009000	SPIS	SPIS1 : S SPIS1 : NS	US	SA	SPI slave 1
9	0x50009000 0x40009000	TWIM	TWIM1 : S TWIM1 : NS	US	SA	Two-wire interface master 1
9	0x50009000 0x40009000	TWIS	TWIS1 : S TWIS1 : NS	US	SA	Two-wire interface slave 1
9	0x50009000 0x40009000	UARTE	UARTE1 : S UARTE1 : NS	US	SA	Universal asynchronous receiver/transmitter with EasyDMA 1
10	0x5000A000 0x4000A000	SPIM	SPIM4 : S SPIM4 : NS	US	SA	SPI master 4 (high-speed)
11	0x5000B000 0x4000B000	SPIM	SPIM2 : S SPIM2 : NS	US	SA	SPI master 2
11	0x5000B000 0x4000B000	SPIS	SPIS2 : S SPIS2 : NS	US	SA	SPI slave 2
11	0x5000B000 0x4000B000	TWIM	TWIM2 : S TWIM2 : NS	US	SA	Two-wire interface master 2
11	0x5000B000 0x4000B000	TWIS	TWIS2 : S TWIS2 : NS	US	SA	Two-wire interface slave 2
11	0x5000B000 0x4000B000	UARTE	UARTE2 : S UARTE2 : NS	US	SA	Universal asynchronous receiver/transmitter with EasyDMA 2
12	0x5000C000 0x4000C000	SPIM	SPIM3 : S SPIM3 : NS	US	SA	SPI master 3
12	0x5000C000 0x4000C000	SPIS	SPIS3 : S SPIS3 : NS	US	SA	SPI slave 3
12	0x5000C000 0x4000C000	TWIM	TWIM3 : S TWIM3 : NS	US	SA	Two-wire interface master 3
12	0x5000C000 0x4000C000	TWIS	TWIS3 : S TWIS3 : NS	US	SA	Two-wire interface slave 3
12	0x5000C000 0x4000C000	UARTE	UARTE3 : S UARTE3 : NS	US	SA	Universal asynchronous receiver/transmitter with EasyDMA 3
13	0x5000D000	GPIOTE	GPIOTE0	S	NA	GPIO tasks and events
14	0x5000E000 0x4000E000	SAADC	SAADC : S SAADC : NS	US	SA	Successive approximation analog-to-digital converter
15	0x5000F000 0x4000F000	TIMER	TIMER0 : S TIMER0 : NS	US	NA	Timer 0
16	0x50010000 0x40010000	TIMER	TIMER1 : S TIMER1 : NS	US	NA	Timer 1
17	0x50011000 0x40011000	TIMER	TIMER2 : S TIMER2 : NS	US	NA	Timer 2
20	0x50014000 0x40014000	RTC	RTC0 : S RTC0 : NS	US	NA	Real time counter 0
21	0x50015000 0x40015000	RTC	RTC1 : S RTC1 : NS	US	NA	Real time counter 1
23	0x50017000 0x40017000	DPPIC	DPPIC : S DPPIC : NS	SPLIT	NA	DPPI controller
24	0x50018000 0x40018000	WDT	WDT0 : S WDT0 : NS	US	NA	Watchdog timer 0
25	0x50019000 0x40019000	WDT	WDT1 : S WDT1 : NS	US	NA	Watchdog timer 1
26	0x5001A000 0x4001A000	COMP	COMP : S COMP : NS	US	NA	Comparator
26	0x5001A000 0x4001A000	LPCOMP	LPCOMP : S LPCOMP : NS	US	NA	Low-power comparator
27	0x5001B000 0x4001B000	EGU	EGU0 : S EGU0 : NS	US	NA	Event generator unit 0
28	0x5001C000 0x4001C000	EGU	EGU1 : S EGU1 : NS	US	NA	Event generator unit 1
29	0x5001D000 0x4001D000	EGU	EGU2 : S EGU2 : NS	US	NA	Event generator unit 2
30	0x5001E000 0x4001E000	EGU	EGU3 : S EGU3 : NS	US	NA	Event generator unit 3
31	0x5001F000 0x4001F000	EGU	EGU4 : S EGU4 : NS	US	NA	Event generator unit 4
32	0x50020000 0x40020000	EGU	EGU5 : S EGU5 : NS	US	NA	Event generator unit 5
33	0x50021000 0x40021000	PWM	PWM0 : S PWM0 : NS	US	SA	Pulse width modulation unit 0
34	0x50022000 0x40022000	PWM	PWM1 : S PWM1 : NS	US	SA	Pulse width modulation unit 1
35	0x50023000 0x40023000	PWM	PWM2 : S PWM2 : NS	US	SA	Pulse width modulation unit 2
36	0x50024000 0x40024000	PWM	PWM3 : S PWM3 : NS	US	SA	Pulse width modulation unit 3
38	0x50026000 0x40026000	PDM	PDM0 : S PDM0 : NS	US	SA	Pulse density modulation (digital microphone) interface
40	0x50028000 0x40028000	I2S	I2S0 : S I2S0 : NS	US	SA	Inter-IC sound interface
42	0x5002A000 0x4002A000	IPC	IPC : S IPC : NS	US	NA	Interprocessor communication
43	0x5002B000 0x4002B000	QSPI	QSPI : S QSPI : NS	US	SA	External memory (quad serial peripheral) interface
45	0x5002D000 0x4002D000	NFCT	NFCT : S NFCT : NS	US	SA	Near field communication tag
47	0x4002F000	GPIOTE	GPIOTE1	NS	NA	GPIO tasks and events
48	0x50030000 0x40030000	MUTEX	MUTEX : S MUTEX : NS	US	NA	Mutual exclusive hardware support
51	0x50033000 0x40033000	QDEC	QDEC0 : S QDEC0 : NS	US	NA	Quadrature decoder 0
52	0x50034000 0x40034000	QDEC	QDEC1 : S QDEC1 : NS	US	NA	Quadrature decoder 1
54	0x50036000 0x40036000	USBD	USBD : S USBD : NS	US	SA	Universal serial bus device
55	0x50037000 0x40037000	USBREG	USBREGULATOR : S USBREGULATOR : NS	US	NA	USB regulator control
57	0x50039000 0x40039000	KMU	KMU : S KMU : NS	SPLIT	NA	Key management unit
57	0x50039000 0x40039000	NVMC	NVMC : S NVMC : NS	SPLIT	NA	Non-volatile memory controller
66	0x50842500 0x40842500	GPIO	P0 : S P0 : NS	SPLIT	NA	General purpose input and output, port 0
66	0x50842800 0x40842800	GPIO	P1 : S P1 : NS	SPLIT	NA	General purpose input and output, port 1
68	0x50844000	CRYPTOCELL	CRYPTOCELL	S	NSA	CryptoCell subsystem control interface
129	0x50081000 0x40081000	VMC	VMC : S VMC : NS	US	NA	Volatile memory controller
N/A	0x00F00000	CACHEDATA	CACHEDATA	S	NA	Cache data
N/A	0x00F08000	CACHEINFO	CACHEINFO	S	NA	Cache info
N/A	0x00FF0000	FICR	FICR	S	NA	Factory information configuration registers
N/A	0x00FF8000	UICR	UICR	S	NA	User information configuration registers
N/A	0xE0042000	CTI	CTI	S	NA	Cross-trigger interface
N/A	0xE0080000	TAD	TAD	S	NA	Trace and debug control