EGU — Event generator unit

Event generator unit (EGU) provides support for interlayer signaling. This means providing support for atomic triggering of both CPU execution and hardware tasks, from both firmware (by CPU) and hardware (by PPI). This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's interrupt service routine (ISR) execution at a lower priority for some of its events. However, triggering any priority from any priority is possible.

Listed here are the main EGU features:

Each instance of EGU implements a set of tasks which can individually be triggered to generate the corresponding event, for example, the corresponding event for TASKS_TRIGGER[n] is EVENTS_TRIGGERED[n]. See Table 1 for a list of EGU instances.

Registers

Table 1. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x5001B000
0x4001B000

APPLICATION EGU

EGU0 : S
EGU0 : NS

US

NA

Event generator unit 0

   

0x5001C000
0x4001C000

APPLICATION EGU

EGU1 : S
EGU1 : NS

US

NA

Event generator unit 1

   

0x5001D000
0x4001D000

APPLICATION EGU

EGU2 : S
EGU2 : NS

US

NA

Event generator unit 2

   

0x5001E000
0x4001E000

APPLICATION EGU

EGU3 : S
EGU3 : NS

US

NA

Event generator unit 3

   

0x5001F000
0x4001F000

APPLICATION EGU

EGU4 : S
EGU4 : NS

US

NA

Event generator unit 4

   

0x50020000
0x40020000

APPLICATION EGU

EGU5 : S
EGU5 : NS

US

NA

Event generator unit 5

   
0x41014000 NETWORK EGU EGU0 NS NA

Event generator unit 0

   
Table 2. Register overview
Register Offset Security Description
TASKS_TRIGGER[n] 0x000  

Trigger n for triggering the corresponding TRIGGERED[n] event

 
SUBSCRIBE_TRIGGER[n] 0x080  

Subscribe configuration for task TRIGGER[n]

 
EVENTS_TRIGGERED[n] 0x100  

Event number n generated by triggering the corresponding TRIGGER[n] task

 
PUBLISH_TRIGGERED[n] 0x180  

Publish configuration for event TRIGGERED[n]

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 

TASKS_TRIGGER[n] (n=0..15)

Address offset: 0x000 + (n × 0x4)

Trigger n for triggering the corresponding TRIGGERED[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_TRIGGER

   

Trigger n for triggering the corresponding TRIGGERED[n] event

     

Trigger

1

Trigger task

SUBSCRIBE_TRIGGER[n] (n=0..15)

Address offset: 0x080 + (n × 0x4)

Subscribe configuration for task TRIGGER[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task TRIGGER[n] will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_TRIGGERED[n] (n=0..15)

Address offset: 0x100 + (n × 0x4)

Event number n generated by triggering the corresponding TRIGGER[n] task

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TRIGGERED

   

Event number n generated by triggering the corresponding TRIGGER[n] task

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_TRIGGERED[n] (n=0..15)

Address offset: 0x180 + (n × 0x4)

Publish configuration for event TRIGGERED[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event TRIGGERED[n] will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-P RW

TRIGGERED[i] (i=0..15)

   

Enable or disable interrupt for event TRIGGERED[i]

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-P RW

TRIGGERED[i] (i=0..15)

   

Write '1' to enable interrupt for event TRIGGERED[i]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-P RW

TRIGGERED[i] (i=0..15)

   

Write '1' to disable interrupt for event TRIGGERED[i]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Electrical specification

EGU Electrical Specification

Symbol Description Min. Typ. Max. Units
tEGU,EVT

Latency between setting an EGU event flag and the system setting an interrupt

.. .. .. cycles

This document was last updated on
2019-12-09.
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