The I2S (Inter-IC Sound) module, supports the original two-channel I2S format, and left- or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.
The I2S peripheral has the following main features:
The I2S protocol specification defines two modes of operation, Master and Slave.
The I2S mode decides which of the two sides (master or slave) shall provide the clock signals LRCK and SCK, and these signals are always supplied by the master to the slave.
The I2S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial data is shifted synchronously to the clock signals SCK and LRCK.
TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. The most significant bit (MSB) is always transmitted first.
TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the CONFIG.TXEN and CONFIG.RXEN.
Transmission and/or reception is started by triggering the START task. With transmission enabled in CONFIG.TXEN), the TXPTRUPD event will be generated for every number of transmitted data words given by RXTXD.MAXCNT. Each data word contains one or more samples. The TXPTRUPD event is generated just before MAXCNT number of data words have been transmitted. Similarly, with reception enabled in CONFIG.RXEN, the RXPTRUPD event will be generated for every received data word given by RXTXD.MAXCNT. The RXPTRUPD event is generated just after MAXCNT number of data words have been received.
SWIDTH | MAXCNT restriction |
---|---|
24Bit | Only even numbers (2,4,6, etc) |
32 | Only even numbers (2, 4, 6, etc) |
24BitIn32 | Only even numbers (2, 4, 6, etc) |
The left right clock (LRCK), often referred to as word clock, sample clock, or word select in I2S context, is the clock defining the frames in serial bitstreams sent and received on SDOUT and SDIN, respectively.
In I2S format, each frame contains one left and/or right sample pair. The left sample is transferred during the low half period of LRCK, followed by the right sample being transferred during the high half period of LRCK.
In Aligned format, each frame contains one left and/or right sample pair. The left sample is transferred during the high half period of LRCK, followed by the right sample being transferred during the low half period of LRCK.
For mono, the frame will contain only zeros for the unused half period of LRCK.
Consequently, the LRCK frequency is equivalent to the audio sample rate.
LRCK = MCK / CONFIG.RATIO
LRCK always toggles around the falling edge of the serial clock SCK.
The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT.
SCK = 2 * LRCK * CONFIG.SWIDTH
The falling edge of the SCK falls on the toggling edge of LRCK.
When operating in Slave mode, SCK is provided by the external I2S master.
The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.
The master clock generator always needs to be enabled when in Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in Slave mode can be useful in the case where the external master is not able to generate its own master clock.
MCK is generated from the clock source selected in the CONFIG.CLKCONFIG and CONFIG.MCKFREQ registers.
The following equation can be used to calculate the value of CONFIG.MCKFREQ for given MCK and clock source frequency:
The parameter fMCK is the requested MCK clock frequency in Hz, and fsource is the frequency of the selected clock source in Hz. Because of rounding errors, an accurate MCK clock may not be achievable. The equation does not take into account the maximum register value of CONFIG.MCKFREQ.
The actual MCK frequency can be calculated using the equation below.
The clock error can be calculated using the equation below. The error e is the percentage difference from the requested fMCK frequency.
The master clock generator does not add any jitter to the clock source chosen.
The master clock generator is enabled/disabled using CONFIG.MCKEN, and the generator is started or stopped by the START or STOP tasks respectively.
In Master mode, the LRCK and the SCK frequencies are closely related as both are derived from MCK and set indirectly through CONFIG.RATIO and CONFIG.SWIDTH.
When configuring these registers, the user is responsible for fulfilling the following requirements:
The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I2S devices that require the MCK to be supplied from the outside.
When operating in Slave mode, the I2S module does not use the MCK and the MCK generator does not need to be enabled.
The clock source for the master clock generator can be selected in the register CONFIG.CLKCONFIG. Choose one of the following clocks as the clock source:
To improve the master clock accuracy and jitter performance, it is recommended (but not mandatory) that the PCLK32M source is running off the HFXO instead of the HFINT oscillator. The ACLK source requires the use of HFXO. See CLOCK — Clock control for more information about starting HFXO for the relevant clock source.
The master clock generator can be bypassed so the MCK clock is derived directly from the input source. This can be configured in the BYPASS field of register CONFIG.CLKCONFIG.
Configuration examples for CLKCONFIG = PCLK32M and Configuration examples for CLKCONFIG = ACLK show some configuration examples for popular sample rates, using both the 32 MHz master clock and the Audio PLL clock source.
Source frequency [Hz] | Requested LRCK [Hz] | RATIO | Requested MCK [Hz] | MCKFREQ | MCK [Hz] | LRCK [Hz] | LRCK error [%] |
---|---|---|---|---|---|---|---|
32000000 | 16000 | 32 | 512000 | 68173824 | 507936 | 15873 | -0.8 |
32000000 | 16000 | 64 | 1024000 | 135274496 | 1032258 | 16129 | 0.8 |
32000000 | 16000 | 256 | 4096000 | 516685824 | 4000000 | 15625 | -2.3 |
32000000 | 32000 | 32 | 1024000 | 135274496 | 1032258 | 32258 | 0.8 |
32000000 | 32000 | 64 | 2048000 | 266350592 | 2000000 | 31250 | -2.3 |
32000000 | 32000 | 256 | 8192000 | 974741504 | 8000000 | 31250 | -2.3 |
32000000 | 44100 | 32 | 1411200 | 185319424 | 1391304 | 43478 | -1.4 |
32000000 | 44100 | 64 | 2822400 | 362815488 | 2909090 | 45455 | 3.1 |
32000000 | 48000 | 32 | 1536000 | 201326592 | 1523809 | 47619 | -0.8 |
32000000 | 48000 | 64 | 3072000 | 393428992 | 3200000 | 50000 | 4.2 |
32000000 | 96000 | 32 | 3072000 | 393428992 | 3200000 | 100000 | 4.2 |
32000000 | 96000 | 64 | 6144000 | 752402432 | 6400000 | 100000 | 4.2 |
Source frequency [Hz] | Requested LRCK [Hz] | RATIO | Requested MCK [Hz] | MCKFREQ | MCK [Hz] | LRCK [Hz] | LRCK error [%] |
---|---|---|---|---|---|---|---|
11289600 | 44100 | 32 | 1411200 | 505286656 | 1411200 | 44100 | 0 |
11289600 | 44100 | 64 | 2822400 | 954433536 | 2822400 | 44100 | 0 |
12288000 | 16000 | 32 | 510000 | 175304704 | 512000 | 16000 | 0 |
12288000 | 16000 | 64 | 1024000 | 343597056 | 1024000 | 16000 | 0 |
12288000 | 32000 | 32 | 1024000 | 343597056 | 1024000 | 32000 | 0 |
12288000 | 32000 | 64 | 2048000 | 660762624 | 2048000 | 32000 | 0 |
12288000 | 48000 | 32 | 1536000 | 505286656 | 1536000 | 48000 | 0 |
12288000 | 48000 | 64 | 3072000 | 954433536 | 3072000 | 48000 | 0 |
12288000 | 96000 | 32 | 3072000 | 954433536 | 3072000 | 96000 | 0 |
In Slave mode, the sample width does not need to equal the half-frame width, or even frame size. This means that there can be extra or fewer SCK pulses per half-frame than what the sample and half-frame widths specified in CONFIG.SWIDTH require.
In cases where left-alignment is used, and the number of SCK pulses per half-frame is higher than the configured width, the following will apply:
In cases where left-alignment is used, and the number of SCK pulses per frame is lower than the word width, the following will apply:
In cases where right-alignment is used, and the number of SCK pulses per frame is higher than the configured width, the following will apply:
In cases where right-alignment is used, and the number of SCK pulses per frame is lower than the configured width, the following will apply:
The I2S module implements EasyDMA for accessing internal Data RAM without CPU intervention.
The source and destination pointers for the TX and RX data are configured in TXD.PTR and RXD.PTR. The memory pointed to by these pointers will only be read or written when TX or RX are enabled in CONFIG.TXEN, and CONFIG.RXEN.
The addresses written to the pointer registers TXD.PTR and RXD.PTR are double-buffered in hardware. These double buffers are updated for every number of transmitted data words given by RXTXD.MAXCNT read from/written to memory. The events TXPTRUPD and RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers.
If TXD.PTR is not pointing to the Data RAM region when transmission is enabled, or RXD.PTR is not pointing to the Data RAM region when reception is enabled, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory for more information about the different memory regions.
Due to the nature of I2S, where the number of transmitted samples always equals the number of received samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in a number of 32-bit words. Such a 32-bit memory word can either contain one 32-bit sample, one right-aligned 24-bit sample sign extended to 32-bit, two 16-bit samples or four 8-bit samples.
In Stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as left and right sample pairs in memory. Memory mapping for 8-bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo., Memory mapping for 16-bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. and Memory mapping for 24-bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. show how the samples are mapped to memory in this mode. The mapping is valid for both RX and TX.
In Mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is stored in memory, the other channel sample is ignored. Memory mapping for 8-bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left., Memory mapping for 16-bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. and Memory mapping for 24-bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. show how RX samples are mapped to memory in this mode. For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame, resulting in a mono output stream.
Described here is a typical operating procedure for the I2S module.
The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I2S module are mapped to physical pins according to the pin numbers specified in the PSEL.x registers.
These pins are acquired whenever the I2S module is enabled through the register ENABLE.
When a pin is acquired by the I2S module, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various I2S pins are shown below in GPIO configuration before enabling peripheral (Master mode) and GPIO configuration before enabling peripheral (Slave mode).
To secure correct signal levels on the pins in System OFF mode, and when the I2S module is disabled, these pins must be configured in the GPIO peripheral directly.
I2S signal | I2S pin | Direction | Output value | Comment |
---|---|---|---|---|
MCK | As specified in PSEL.MCK | Output | 0 | |
LRCK | As specified in PSEL.LRCK | Output | 0 | |
SCK | As specified in PSEL.SCK | Output | 0 | |
SDIN | As specified in PSEL.SDIN | Input | Not applicable | |
SDOUT | As specified in PSEL.SDOUT | Output | 0 |
I2S signal | I2S pin | Direction | Output value | Comment |
---|---|---|---|---|
MCK | As specified in PSEL.MCK | Output | 0 | |
LRCK | As specified in PSEL.LRCK | Input | Not applicable | |
SCK | As specified in PSEL.SCK | Input | Not applicable | |
SDIN | As specified in PSEL.SDIN | Input | Not applicable | |
SDOUT | As specified in PSEL.SDOUT | Output | 0 |
Base address | Domain | Peripheral | Instance | Secure mapping | DMA security | Description | Configuration | |
---|---|---|---|---|---|---|---|---|
0x50028000 |
APPLICATION | I2S |
I2S0 : S |
US |
SA |
Inter-IC sound interface |
Register | Offset | Security | Description | |
---|---|---|---|---|
TASKS_START | 0x000 |
Starts continuous I2S transfer. Also starts MCK generator when this is enabled |
||
TASKS_STOP | 0x004 |
Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. |
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SUBSCRIBE_START | 0x080 |
Subscribe configuration for task START |
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SUBSCRIBE_STOP | 0x084 |
Subscribe configuration for task STOP |
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EVENTS_RXPTRUPD | 0x104 |
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. |
||
EVENTS_STOPPED | 0x108 |
I2S transfer stopped. |
||
EVENTS_TXPTRUPD | 0x114 |
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. |
||
EVENTS_FRAMESTART | 0x11C |
Frame start event, generated on the active edge of LRCK |
||
PUBLISH_RXPTRUPD | 0x184 |
Publish configuration for event RXPTRUPD |
||
PUBLISH_STOPPED | 0x188 |
Publish configuration for event STOPPED |
||
PUBLISH_TXPTRUPD | 0x194 |
Publish configuration for event TXPTRUPD |
||
PUBLISH_FRAMESTART | 0x19C |
Publish configuration for event FRAMESTART |
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INTEN | 0x300 |
Enable or disable interrupt |
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INTENSET | 0x304 |
Enable interrupt |
||
INTENCLR | 0x308 |
Disable interrupt |
||
ENABLE | 0x500 |
Enable I2S module |
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CONFIG.MODE | 0x504 |
I2S mode |
||
CONFIG.RXEN | 0x508 |
Reception (RX) enable |
||
CONFIG.TXEN | 0x50C |
Transmission (TX) enable |
||
CONFIG.MCKEN | 0x510 |
Master clock generator enable |
||
CONFIG.MCKFREQ | 0x514 |
I2S clock generator control |
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CONFIG.RATIO | 0x518 |
MCK / LRCK ratio |
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CONFIG.SWIDTH | 0x51C |
Sample width |
||
CONFIG.ALIGN | 0x520 |
Alignment of sample within a frame |
||
CONFIG.FORMAT | 0x524 |
Frame format |
||
CONFIG.CHANNELS | 0x528 |
Enable channels |
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CONFIG.CLKCONFIG | 0x52C |
Clock source selection for the I2S module |
||
RXD.PTR | 0x538 |
Receive buffer RAM start address. |
||
TXD.PTR | 0x540 |
Transmit buffer RAM start address |
||
RXTXD.MAXCNT | 0x550 |
Size of RXD and TXD buffers |
||
PSEL.MCK | 0x560 |
Pin select for MCK signal |
||
PSEL.SCK | 0x564 |
Pin select for SCK signal |
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PSEL.LRCK | 0x568 |
Pin select for LRCK signal |
||
PSEL.SDIN | 0x56C |
Pin select for SDIN signal |
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PSEL.SDOUT | 0x570 |
Pin select for SDOUT signal |
Address offset: 0x000
Starts continuous I2S transfer. Also starts MCK generator when this is enabled
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_START |
Starts continuous I2S transfer. Also starts MCK generator when this is enabled |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x004
Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_STOP |
Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. |
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Trigger |
1 |
Trigger task |
Address offset: 0x080
Subscribe configuration for task START
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that task START will subscribe to |
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B | RW |
EN |
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Disabled |
0 |
Disable subscription |
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Enabled |
1 |
Enable subscription |
Address offset: 0x084
Subscribe configuration for task STOP
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that task STOP will subscribe to |
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B | RW |
EN |
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Disabled |
0 |
Disable subscription |
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Enabled |
1 |
Enable subscription |
Address offset: 0x104
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_RXPTRUPD |
The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. |
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NotGenerated |
0 |
Event not generated |
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Generated |
1 |
Event generated |
Address offset: 0x108
I2S transfer stopped.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_STOPPED |
I2S transfer stopped. |
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NotGenerated |
0 |
Event not generated |
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Generated |
1 |
Event generated |
Address offset: 0x114
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_TXPTRUPD |
The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. |
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NotGenerated |
0 |
Event not generated |
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Generated |
1 |
Event generated |
Address offset: 0x11C
Frame start event, generated on the active edge of LRCK
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
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Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_FRAMESTART |
Frame start event, generated on the active edge of LRCK |
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NotGenerated |
0 |
Event not generated |
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Generated |
1 |
Event generated |
Address offset: 0x184
Publish configuration for event RXPTRUPD
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that event RXPTRUPD will publish to. |
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B | RW |
EN |
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Disabled |
0 |
Disable publishing |
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Enabled |
1 |
Enable publishing |
Address offset: 0x188
Publish configuration for event STOPPED
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that event STOPPED will publish to. |
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B | RW |
EN |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable publishing |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable publishing |
Address offset: 0x194
Publish configuration for event TXPTRUPD
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that event TXPTRUPD will publish to. |
|||||||||||||||||||||||||||||||
B | RW |
EN |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable publishing |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable publishing |
Address offset: 0x19C
Publish configuration for event FRAMESTART
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | B | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHIDX |
[255..0] |
DPPI channel that event FRAMESTART will publish to. |
|||||||||||||||||||||||||||||||
B | RW |
EN |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable publishing |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable publishing |
Address offset: 0x300
Enable or disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
H |
F | C | B | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
B | RW |
RXPTRUPD |
Enable or disable interrupt for event RXPTRUPD |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
C | RW |
STOPPED |
Enable or disable interrupt for event STOPPED |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
F | RW |
TXPTRUPD |
Enable or disable interrupt for event TXPTRUPD |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
H | RW |
FRAMESTART |
Enable or disable interrupt for event FRAMESTART |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
H |
F | C | B | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
B | RW |
RXPTRUPD |
Write '1' to enable interrupt for event RXPTRUPD |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
STOPPED |
Write '1' to enable interrupt for event STOPPED |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
TXPTRUPD |
Write '1' to enable interrupt for event TXPTRUPD |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
H | RW |
FRAMESTART |
Write '1' to enable interrupt for event FRAMESTART |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
H |
F | C | B | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
B | RW |
RXPTRUPD |
Write '1' to disable interrupt for event RXPTRUPD |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
STOPPED |
Write '1' to disable interrupt for event STOPPED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
TXPTRUPD |
Write '1' to disable interrupt for event TXPTRUPD |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
H | RW |
FRAMESTART |
Write '1' to disable interrupt for event FRAMESTART |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
Address offset: 0x500
Enable I2S module
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable I2S module |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
Address offset: 0x504
I2S mode
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MODE |
I2S mode |
||||||||||||||||||||||||||||||||
Master |
0 |
Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. |
|||||||||||||||||||||||||||||||||
Slave |
1 |
Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx |
Address offset: 0x508
Reception (RX) enable
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
RXEN |
Reception (RX) enable |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Reception disabled and now data will be written to the RXD.PTR address. |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Reception enabled. |
Address offset: 0x50C
Transmission (TX) enable
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TXEN |
Transmission (TX) enable |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Transmission disabled and now data will be read from the RXD.TXD address. |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Transmission enabled. |
Address offset: 0x510
Master clock generator enable
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MCKEN |
Master clock generator enable |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Master clock generator disabled and PSEL.MCK not connected(available as GPIO). |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Master clock generator running and MCK output on PSEL.MCK. |
Address offset: 0x514
I2S clock generator control
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x20000000 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MCKFREQ |
I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero. |
||||||||||||||||||||||||||||||||
32MDIV2 |
0x80000000 |
32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV3 |
0x50000000 |
32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV4 |
0x40000000 |
32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV5 |
0x30000000 |
32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV6 |
0x28000000 |
32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV8 |
0x20000000 |
32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV10 |
0x18000000 |
32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV11 |
0x16000000 |
32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV15 |
0x11000000 |
32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV16 |
0x10000000 |
32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV21 |
0x0C000000 |
32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV23 |
0x0B000000 |
32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV30 |
0x08800000 |
32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV31 |
0x08400000 |
32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV32 |
0x08000000 |
32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV42 |
0x06000000 |
32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV63 |
0x04100000 |
32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation. |
|||||||||||||||||||||||||||||||||
32MDIV125 |
0x020C0000 |
32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation. |
Address offset: 0x518
MCK / LRCK ratio
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000006 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
RATIO |
MCK / LRCK ratio |
||||||||||||||||||||||||||||||||
32X |
0 |
LRCK = MCK / 32 |
|||||||||||||||||||||||||||||||||
48X |
1 |
LRCK = MCK / 48 |
|||||||||||||||||||||||||||||||||
64X |
2 |
LRCK = MCK / 64 |
|||||||||||||||||||||||||||||||||
96X |
3 |
LRCK = MCK / 96 |
|||||||||||||||||||||||||||||||||
128X |
4 |
LRCK = MCK / 128 |
|||||||||||||||||||||||||||||||||
192X |
5 |
LRCK = MCK / 192 |
|||||||||||||||||||||||||||||||||
256X |
6 |
LRCK = MCK / 256 |
|||||||||||||||||||||||||||||||||
384X |
7 |
LRCK = MCK / 384 |
|||||||||||||||||||||||||||||||||
512X |
8 |
LRCK = MCK / 512 |
Address offset: 0x51C
Sample width
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
SWIDTH |
Sample and half-frame width |
||||||||||||||||||||||||||||||||
8Bit |
0 |
8 bit sample. |
|||||||||||||||||||||||||||||||||
16Bit |
1 |
16 bit sample. |
|||||||||||||||||||||||||||||||||
24Bit |
2 |
24 bit sample. |
|||||||||||||||||||||||||||||||||
32Bit |
3 |
32 bit sample. |
|||||||||||||||||||||||||||||||||
8BitIn16 |
4 |
8 bit sample in a 16-bit half-frame. |
|||||||||||||||||||||||||||||||||
8BitIn32 |
5 |
8 bit sample in a 32-bit half-frame. |
|||||||||||||||||||||||||||||||||
16BitIn32 |
6 |
16 bit sample in a 32-bit half-frame. |
|||||||||||||||||||||||||||||||||
24BitIn32 |
7 |
24 bit sample in a 32-bit half-frame. |
Address offset: 0x520
Alignment of sample within a frame
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ALIGN |
Alignment of sample within a frame |
||||||||||||||||||||||||||||||||
Left |
0 |
Left-aligned. |
|||||||||||||||||||||||||||||||||
Right |
1 |
Right-aligned. |
Address offset: 0x524
Frame format
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
FORMAT |
Frame format |
||||||||||||||||||||||||||||||||
I2S |
0 |
Original I2S format. |
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Aligned |
1 |
Alternate (left- or right-aligned) format. |
Address offset: 0x528
Enable channels
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | |||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CHANNELS |
Enable channels |
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Stereo |
0 |
Stereo. |
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Left |
1 |
Left only. |
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Right |
2 |
Right only. |
Address offset: 0x52C
Clock source selection for the I2S module
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
B |
A | |||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CLKSRC |
Clock source selection |
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PCLK32M |
0 |
32MHz peripheral clock |
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ACLK |
1 |
Audio PLL clock |
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B | RW |
BYPASS |
Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect. |
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Disable |
0 |
Disable bypass |
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Enable |
1 |
Enable bypass |
Address offset: 0x538
Receive buffer RAM start address.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA.
|
Address offset: 0x540
Transmit buffer RAM start address
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA.
|
Address offset: 0x550
Size of RXD and TXD buffers
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXCNT |
Size of RXD and TXD buffers in number of 32 bit words |
Address offset: 0x560
Pin select for MCK signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | C |
B |
A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
PORT |
[0..1] |
Port number |
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C | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
Address offset: 0x564
Pin select for SCK signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | C |
B |
A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
PORT |
[0..1] |
Port number |
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C | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
Address offset: 0x568
Pin select for LRCK signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | C |
B |
A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
PORT |
[0..1] |
Port number |
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C | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
Address offset: 0x56C
Pin select for SDIN signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | C |
B |
A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
PORT |
[0..1] |
Port number |
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C | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
Address offset: 0x570
Pin select for SDOUT signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | C |
B |
A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
PORT |
[0..1] |
Port number |
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C | RW |
CONNECT |
Connection |
||||||||||||||||||||||||||||||||
Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
tS_SDIN |
SDIN setup time before SCK rising |
20 | ns | ||||||
tH_SDIN |
SDIN hold time after SCK rising |
15 | ns | ||||||
tS_SDOUT |
SDOUT setup time after SCK falling |
50 | ns | ||||||
tH_SDOUT |
SDOUT hold time after SCK falling |
13 | ns | ||||||
tSCK_LRCK |
SCLK falling to LRCK edge |
-5 | 0 | 5 | ns | ||||
fMCK |
MCK frequency |
12288 | kHz | ||||||
fLRCK |
LRCK frequency |
96 | kHz | ||||||
fSCK |
SCK frequency |
8000 | kHz | ||||||
DCCK |
Clock duty cycle (MCK, LRCK, SCK) |
45 | 55 | % |