UARTE — Universal asynchronous receiver/transmitter with EasyDMA

The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM.

Listed here are the main features for UARTE:

Figure 1. UARTE configuration
UARTE configuration

The GPIOs used for each UART interface can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing.

Note: External crystal oscillator must be enabled to obtain sufficient clock accuracy for stable communication. See CLOCK — Clock control for more information.

EasyDMA

The UARTE implements EasyDMA for reading and writing to and from the RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX buffer in RAM.

Transmission

The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task.

After each byte has been sent over the TXD line, a TXDRDY event will be generated.

When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the UARTE transmission will end automatically and an ENDTX event will be generated.

A UARTE transmission sequence is stopped by triggering the STOPTX task, a TXSTOPPED event will be generated when the UARTE transmitter has stopped.

If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have not been transmitted.

If flow control is enabled through the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is deactivated and resumed when CTS is activated again, as illustrated in Figure 2. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended.

Figure 2. UARTE transmission
UARTE transmission

The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the TXSTOPPED event has been generated. See POWER — Power control for more information about power modes.

Reception

The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to store incoming data in an RX buffer in RAM.

The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is double-buffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register and the UARTE will generate an ENDRX event when it has filled up the RX buffer, see Figure 3.

For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM.

The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have been transferred to the RX buffer in RAM since the previous ENDRX event.

Figure 3. UARTE reception
UARTE reception

The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated.

Important: If the ENDRX event has not already been generated when the UARTE receiver has come to a stop, which implies that all pending content in the RX FIFO has been moved to the RX buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not full. In this scenario the ENDRX event will be generated before the RXTO event is generated.

To be able to know how many bytes have actually been received into the RX buffer, the CPU can read the RXD.AMOUNT register following the ENDRX event or the RXTO event.

The UARTE is able to receive up to four bytes after the STOPRX task has been triggered as long as these are sent in succession immediately after the RTS signal is deactivated. This is possible because after the RTS is deactivated the UARTE is able to receive bytes for an extended period equal to the time it takes to send 4 bytes on the configured baud rate.

After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered. To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, see Figure 4. The UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.

Figure 4. UARTE reception with forced stop via STOPRX
UARTE reception with forced stop via STOPRX

If HW flow control is enabled through the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.

With flow control disabled, the UARTE will function in the same way as when the flow control is enabled except that the RTS line will not be used. This means that no signal will be generated when the UARTE has reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost.

The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event has been generated. See POWER — Power control for more information about power modes.

Error conditions

An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs.

An ERROR event will not stop reception. If the error was a parity error, the received byte will still be transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit), that specific byte will NOT be stored into Data RAM, but following incoming bytes will.

Using the UARTE without flow control

If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time.

Parity and stop bit configuration

Automatic even parity generation for both transmission and reception can be configured using the register CONFIG. If odd parity is desired, it can be configured using the register CONFIG. See the register description for details.

The amount of stop bits can also be configured through the register CONFIG.

Low power

When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.

The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling the peripheral through the ENABLE register.

Pin configuration

The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UARTE are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.

The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.RTS, PSEL.RTS and PSEL.TXD must only be configured when the UARTE is disabled.

To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in Table 1.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.

Table 1. GPIO configuration before enabling peripheral
UARTE signal UARTE pin Direction Output value
RXD As specified in PSEL.RXD Input Not applicable
CTS As specified in PSEL.CTS Input Not applicable
RTS As specified in PSEL.RTS Output 1
TXD As specified in PSEL.TXD Output 1

Registers

Table 2. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50008000
0x40008000

APPLICATION UARTE

UARTE0 : S
UARTE0 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 0

   

0x50009000
0x40009000

APPLICATION UARTE

UARTE1 : S
UARTE1 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 1

   

0x5000B000
0x4000B000

APPLICATION UARTE

UARTE2 : S
UARTE2 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 2

   

0x5000C000
0x4000C000

APPLICATION UARTE

UARTE3 : S
UARTE3 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 3

   
0x41013000 NETWORK UARTE UARTE0 NS NA

Universal asynchronous receiver/transmitter

   
Table 3. Register overview
Register Offset Security Description
TASKS_STARTRX 0x000  

Start UART receiver

 
TASKS_STOPRX 0x004  

Stop UART receiver

 
TASKS_STARTTX 0x008  

Start UART transmitter

 
TASKS_STOPTX 0x00C  

Stop UART transmitter

 
TASKS_FLUSHRX 0x02C  

Flush RX FIFO into RX buffer

 
SUBSCRIBE_STARTRX 0x080  

Subscribe configuration for task STARTRX

 
SUBSCRIBE_STOPRX 0x084  

Subscribe configuration for task STOPRX

 
SUBSCRIBE_STARTTX 0x088  

Subscribe configuration for task STARTTX

 
SUBSCRIBE_STOPTX 0x08C  

Subscribe configuration for task STOPTX

 
SUBSCRIBE_FLUSHRX 0x0AC  

Subscribe configuration for task FLUSHRX

 
EVENTS_CTS 0x100  

CTS is activated (set low). Clear To Send.

 
EVENTS_NCTS 0x104  

CTS is deactivated (set high). Not Clear To Send.

 
EVENTS_RXDRDY 0x108  

Data received in RXD (but potentially not yet transferred to Data RAM)

 
EVENTS_ENDRX 0x110  

Receive buffer is filled up

 
EVENTS_TXDRDY 0x11C  

Data sent from TXD

 
EVENTS_ENDTX 0x120  

Last TX byte transmitted

 
EVENTS_ERROR 0x124  

Error detected

 
EVENTS_RXTO 0x144  

Receiver timeout

 
EVENTS_RXSTARTED 0x14C  

UART receiver has started

 
EVENTS_TXSTARTED 0x150  

UART transmitter has started

 
EVENTS_TXSTOPPED 0x158  

Transmitter stopped

 
PUBLISH_CTS 0x180  

Publish configuration for event CTS

 
PUBLISH_NCTS 0x184  

Publish configuration for event NCTS

 
PUBLISH_RXDRDY 0x188  

Publish configuration for event RXDRDY

 
PUBLISH_ENDRX 0x190  

Publish configuration for event ENDRX

 
PUBLISH_TXDRDY 0x19C  

Publish configuration for event TXDRDY

 
PUBLISH_ENDTX 0x1A0  

Publish configuration for event ENDTX

 
PUBLISH_ERROR 0x1A4  

Publish configuration for event ERROR

 
PUBLISH_RXTO 0x1C4  

Publish configuration for event RXTO

 
PUBLISH_RXSTARTED 0x1CC  

Publish configuration for event RXSTARTED

 
PUBLISH_TXSTARTED 0x1D0  

Publish configuration for event TXSTARTED

 
PUBLISH_TXSTOPPED 0x1D8  

Publish configuration for event TXSTOPPED

 
SHORTS 0x200  

Shortcuts between local events and tasks

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
ERRORSRC 0x480  

Error source

Note : this register is read / write one to clear.

 
ENABLE 0x500  

Enable UART

 
PSEL.RTS 0x508  

Pin select for RTS signal

 
PSEL.TXD 0x50C  

Pin select for TXD signal

 
PSEL.CTS 0x510  

Pin select for CTS signal

 
PSEL.RXD 0x514  

Pin select for RXD signal

 
BAUDRATE 0x524  

Baud rate. Accuracy depends on the HFCLK source selected.

 
RXD.PTR 0x534  

Data pointer

 
RXD.MAXCNT 0x538  

Maximum number of bytes in receive buffer

 
RXD.AMOUNT 0x53C  

Number of bytes transferred in the last transaction

 
TXD.PTR 0x544  

Data pointer

 
TXD.MAXCNT 0x548  

Maximum number of bytes in transmit buffer

 
TXD.AMOUNT 0x54C  

Number of bytes transferred in the last transaction

 
CONFIG 0x56C  

Configuration of parity and hardware flow control

 

TASKS_STARTRX

Address offset: 0x000

Start UART receiver

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STARTRX

   

Start UART receiver

     

Trigger

1

Trigger task

TASKS_STOPRX

Address offset: 0x004

Stop UART receiver

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOPRX

   

Stop UART receiver

     

Trigger

1

Trigger task

TASKS_STARTTX

Address offset: 0x008

Start UART transmitter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STARTTX

   

Start UART transmitter

     

Trigger

1

Trigger task

TASKS_STOPTX

Address offset: 0x00C

Stop UART transmitter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOPTX

   

Stop UART transmitter

     

Trigger

1

Trigger task

TASKS_FLUSHRX

Address offset: 0x02C

Flush RX FIFO into RX buffer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_FLUSHRX

   

Flush RX FIFO into RX buffer

     

Trigger

1

Trigger task

SUBSCRIBE_STARTRX

Address offset: 0x080

Subscribe configuration for task STARTRX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task STARTRX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOPRX

Address offset: 0x084

Subscribe configuration for task STOPRX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task STOPRX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STARTTX

Address offset: 0x088

Subscribe configuration for task STARTTX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task STARTTX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOPTX

Address offset: 0x08C

Subscribe configuration for task STOPTX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task STOPTX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_FLUSHRX

Address offset: 0x0AC

Subscribe configuration for task FLUSHRX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task FLUSHRX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_CTS

Address offset: 0x100

CTS is activated (set low). Clear To Send.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_CTS

   

CTS is activated (set low). Clear To Send.

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_NCTS

Address offset: 0x104

CTS is deactivated (set high). Not Clear To Send.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_NCTS

   

CTS is deactivated (set high). Not Clear To Send.

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_RXDRDY

Address offset: 0x108

Data received in RXD (but potentially not yet transferred to Data RAM)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RXDRDY

   

Data received in RXD (but potentially not yet transferred to Data RAM)

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_ENDRX

Address offset: 0x110

Receive buffer is filled up

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_ENDRX

   

Receive buffer is filled up

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_TXDRDY

Address offset: 0x11C

Data sent from TXD

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TXDRDY

   

Data sent from TXD

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_ENDTX

Address offset: 0x120

Last TX byte transmitted

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_ENDTX

   

Last TX byte transmitted

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_ERROR

Address offset: 0x124

Error detected

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_ERROR

   

Error detected

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_RXTO

Address offset: 0x144

Receiver timeout

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RXTO

   

Receiver timeout

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_RXSTARTED

Address offset: 0x14C

UART receiver has started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RXSTARTED

   

UART receiver has started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_TXSTARTED

Address offset: 0x150

UART transmitter has started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TXSTARTED

   

UART transmitter has started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_TXSTOPPED

Address offset: 0x158

Transmitter stopped

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TXSTOPPED

   

Transmitter stopped

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_CTS

Address offset: 0x180

Publish configuration for event CTS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event CTS will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_NCTS

Address offset: 0x184

Publish configuration for event NCTS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event NCTS will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_RXDRDY

Address offset: 0x188

Publish configuration for event RXDRDY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event RXDRDY will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_ENDRX

Address offset: 0x190

Publish configuration for event ENDRX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event ENDRX will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_TXDRDY

Address offset: 0x19C

Publish configuration for event TXDRDY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event TXDRDY will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_ENDTX

Address offset: 0x1A0

Publish configuration for event ENDTX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event ENDTX will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_ERROR

Address offset: 0x1A4

Publish configuration for event ERROR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event ERROR will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_RXTO

Address offset: 0x1C4

Publish configuration for event RXTO

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event RXTO will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_RXSTARTED

Address offset: 0x1CC

Publish configuration for event RXSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event RXSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_TXSTARTED

Address offset: 0x1D0

Publish configuration for event TXSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event TXSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_TXSTOPPED

Address offset: 0x1D8

Publish configuration for event TXSTOPPED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event TXSTOPPED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                   D C      
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
C RW

ENDRX_STARTRX

   

Shortcut between event ENDRX and task STARTRX

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

ENDRX_STOPRX

   

Shortcut between event ENDRX and task STOPRX

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                   L J I   H               G F E     D   C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CTS

   

Enable or disable interrupt for event CTS

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

NCTS

   

Enable or disable interrupt for event NCTS

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

RXDRDY

   

Enable or disable interrupt for event RXDRDY

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

ENDRX

   

Enable or disable interrupt for event ENDRX

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

TXDRDY

   

Enable or disable interrupt for event TXDRDY

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

ENDTX

   

Enable or disable interrupt for event ENDTX

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

ERROR

   

Enable or disable interrupt for event ERROR

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

RXTO