LPCOMP — Low-power comparator

Low-power comparator (LPCOMP) compares an input voltage against a reference voltage.

Listed here are the main features of LPCOMP:

In System ON, the LPCOMP can generate separate events on rising and falling edges of a signal, or sample the current state of the pin as being above or below the selected reference. The block can be configured to use any of the analog inputs on the device. Additionally, the low-power comparator can be used as an analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a range of fractions of the supply voltage.

Note: LPCOMP cannot be used (STARTed) at the same time as COMP. Only one comparator can be used at a time.
Figure 1. Low-power comparator
Low-power comparator

The wakeup comparator (LPCOMP) compares an input voltage (VIN+), which comes from an analog input pin selected via the PSEL register, against a reference voltage (VIN-) selected via registers REFSEL and EXTREFSEL.

The PSEL, REFSEL, and EXTREFSEL registers must be configured before the LPCOMP is enabled through the ENABLE register.

The HYST register allows enabling an optional hysteresis in the comparator core. This hysteresis shall prevent noise on the signal to create unwanted events. Figure below illustrates the effect of an active hysteresis on a noisy input signal. It is disabled by default, and shall be configured before enabling LPCOMP as well.

Figure 2. Effect of hysteresis on a noisy input signal
Effect of hysteresis on a noisy input signal

The LPCOMP is started by triggering the START task. After a startup time of tLPCOMP,STARTUP, the LPCOMP will generate a READY event to indicate that the comparator is ready to use and the output of the LPCOMP is correct. The LPCOMP will generate events every time VIN+ crosses VIN-. More specifically, every time VIN+ rises above VIN- (upward crossing) an UP event is generated along with a CROSS event. Every time VIN+ falls below VIN- (downward crossing), a DOWN event is generated along with a CROSS event. When hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing level becomes (VIN- - VHYST/2).

The LPCOMP is stopped by triggering the STOP task.

LPCOMP will be operational in both System ON and System OFF mode when it is enabled through the ENABLE register. See POWER — Power control for more information about power modes. Note that it is not allowed to go to System OFF when a READY event is pending to be generated.

All LPCOMP registers, including ENABLE, are classified as retained registers when the LPCOMP is enabled. However, when the device wakes up from System OFF, all LPCOMP registers will be reset.

The LPCOMP can wake up the system from System OFF by asserting the ANADETECT signal. The ANADETECT signal can be derived from any of the event sources that generate the UP, DOWN and CROSS events. In case of wakeup from System OFF, no events will be generated, only the ANADETECT signal. See the ANADETECT register (ANADETECT) for more information on how to configure the ANADETECT signal.

The immediate value of the LPCOMP can be sampled to RESULT by triggering the SAMPLE task.

See RESETREAS for more information on how to detect a wakeup from LPCOMP.

Shared resources

The LPCOMP shares analog resources with SAADC. While it is possible to use the SAADC at the same time as the LPCOMP, selecting the same analog input pin for both modules is not supported.

Additionally, LPCOMP shares registers and other resources with other peripherals that have the same ID as the LPCOMP. See Peripherals with shared ID for more information.

The LPCOMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has been stopped. Failing to do so may result in unpredictable behavior.

Pin configuration

You can use the LPCOMP.PSEL register to select one of the analog input pins, AIN0 through AIN7, as the analog input pin for the LPCOMP.

See GPIO — General purpose input/output for more information about the pins. Similarly, you can use EXTREFSEL to select one of the analog reference input pins, AIN0 and AIN1, as input for AREF in case AREF is selected in EXTREFSEL. The selected analog pins will be acquired by the LPCOMP when it is enabled through ENABLE.

Registers

Table 1. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x5001A000
0x4001A000

APPLICATION LPCOMP

LPCOMP : S
LPCOMP : NS

US

NA

Low-power comparator

   
Table 2. Register overview
Register Offset Security Description
TASKS_START 0x000  

Start comparator

 
TASKS_STOP 0x004  

Stop comparator

 
TASKS_SAMPLE 0x008  

Sample comparator value

 
SUBSCRIBE_START 0x080  

Subscribe configuration for task START

 
SUBSCRIBE_STOP 0x084  

Subscribe configuration for task STOP

 
SUBSCRIBE_SAMPLE 0x088  

Subscribe configuration for task SAMPLE

 
EVENTS_READY 0x100  

LPCOMP is ready and output is valid

 
EVENTS_DOWN 0x104  

Downward crossing

 
EVENTS_UP 0x108  

Upward crossing

 
EVENTS_CROSS 0x10C  

Downward or upward crossing

 
PUBLISH_READY 0x180  

Publish configuration for event READY

 
PUBLISH_DOWN 0x184  

Publish configuration for event DOWN

 
PUBLISH_UP 0x188  

Publish configuration for event UP

 
PUBLISH_CROSS 0x18C  

Publish configuration for event CROSS

 
SHORTS 0x200  

Shortcuts between local events and tasks

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
RESULT 0x400  

Compare result

 
ENABLE 0x500  

Enable LPCOMP

 
PSEL 0x504  

Input pin select

 
REFSEL 0x508  

Reference select

 
EXTREFSEL 0x50C  

External reference select

 
ANADETECT 0x520  

Analog detect configuration

 
HYST 0x538  

Comparator hysteresis enable

 

TASKS_START

Address offset: 0x000

Start comparator

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_START

   

Start comparator

     

Trigger

1

Trigger task

TASKS_STOP

Address offset: 0x004

Stop comparator

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOP

   

Stop comparator

     

Trigger

1

Trigger task

TASKS_SAMPLE

Address offset: 0x008

Sample comparator value

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_SAMPLE

   

Sample comparator value

     

Trigger

1

Trigger task

SUBSCRIBE_START

Address offset: 0x080

Subscribe configuration for task START

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task START will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOP

Address offset: 0x084

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task STOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_SAMPLE

Address offset: 0x088

Subscribe configuration for task SAMPLE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that task SAMPLE will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_READY

Address offset: 0x100

LPCOMP is ready and output is valid

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_READY

   

LPCOMP is ready and output is valid

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_DOWN

Address offset: 0x104

Downward crossing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_DOWN

   

Downward crossing

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_UP

Address offset: 0x108

Upward crossing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_UP

   

Upward crossing

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_CROSS

Address offset: 0x10C

Downward or upward crossing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_CROSS

   

Downward or upward crossing

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_READY

Address offset: 0x180

Publish configuration for event READY

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event READY will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_DOWN

Address offset: 0x184

Publish configuration for event DOWN

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event DOWN will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_UP

Address offset: 0x188

Publish configuration for event UP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event UP will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_CROSS

Address offset: 0x18C

Publish configuration for event CROSS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                               A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[255..0]

Channel that event CROSS will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                       E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY_SAMPLE

   

Shortcut between event READY and task SAMPLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

READY_STOP

   

Shortcut between event READY and task STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

C RW

DOWN_STOP

   

Shortcut between event DOWN and task STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

UP_STOP

   

Shortcut between event UP and task STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

E RW

CROSS_STOP

   

Shortcut between event CROSS and task STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY

   

Write '1' to enable interrupt for event READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to enable interrupt for event DOWN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to enable interrupt for event UP

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to enable interrupt for event CROSS

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

READY

   

Write '1' to disable interrupt for event READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to disable interrupt for event DOWN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to disable interrupt for event UP

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to disable interrupt for event CROSS

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

RESULT

Address offset: 0x400

Compare result

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

RESULT

   

Result of last compare. Decision point SAMPLE task.

     

Below

0

Input voltage is below the reference threshold (VIN+ < VIN-)

     

Above

1

Input voltage is above the reference threshold (VIN+ > VIN-)

ENABLE

Address offset: 0x500

Enable LPCOMP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ENABLE

   

Enable or disable LPCOMP

     

Disabled

0

Disable

     

Enabled

1

Enable

PSEL

Address offset: 0x504

Input pin select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                           A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

PSEL

   

Analog pin select

     

AnalogInput0

0

AIN0 selected as analog input

     

AnalogInput1

1

AIN1 selected as analog input

     

AnalogInput2

2

AIN2 selected as analog input

     

AnalogInput3

3

AIN3 selected as analog input

     

AnalogInput4

4

AIN4 selected as analog input

     

AnalogInput5

5

AIN5 selected as analog input

     

AnalogInput6

6

AIN6 selected as analog input

     

AnalogInput7

7

AIN7 selected as analog input

REFSEL

Address offset: 0x508

Reference select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         A A A A
Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ID Access Field Value ID Value Description
A RW

REFSEL

   

Reference select

     

Ref1_8Vdd

0

VDD * 1/8 selected as reference

     

Ref2_8Vdd

1

VDD * 2/8 selected as reference

     

Ref3_8Vdd

2

VDD * 3/8 selected as reference

     

Ref4_8Vdd

3

VDD * 4/8 selected as reference

     

Ref5_8Vdd

4

VDD * 5/8 selected as reference

     

Ref6_8Vdd

5

VDD * 6/8 selected as reference

     

Ref7_8Vdd

6

VDD * 7/8 selected as reference

     

ARef

7

External analog reference selected

     

Ref1_16Vdd

8

VDD * 1/16 selected as reference

     

Ref3_16Vdd

9

VDD * 3/16 selected as reference

     

Ref5_16Vdd

10

VDD * 5/16 selected as reference

     

Ref7_16Vdd

11

VDD * 7/16 selected as reference

     

Ref9_16Vdd

12

VDD * 9/16 selected as reference

     

Ref11_16Vdd

13

VDD * 11/16 selected as reference

     

Ref13_16Vdd

14

VDD * 13/16 selected as reference

     

Ref15_16Vdd

15

VDD * 15/16 selected as reference

EXTREFSEL

Address offset: 0x50C

External reference select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                           A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EXTREFSEL

   

External analog reference select

     

AnalogReference0

0

Use AIN0 as external analog reference

     

AnalogReference1

1

Use AIN1 as external analog reference

ANADETECT

Address offset: 0x520

Analog detect configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ANADETECT

   

Analog detect configuration

     

Cross

0

Generate ANADETECT on crossing, both upward crossing and downward crossing

     

Up

1

Generate ANADETECT on upward crossing only

     

Down

2

Generate ANADETECT on downward crossing only

HYST

Address offset: 0x538

Comparator hysteresis enable

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

HYST

   

Comparator hysteresis enable

     

Disabled

0

Comparator hysteresis disabled

     

Enabled

1

Comparator hysteresis enabled

Electrical specification

LPCOMP Electrical Specification

Symbol Description Min. Typ. Max. Units
tLPCANADET

Time from VIN crossing (>=50 mV above threshold) to ANADETECT signal generated

.. .. .. µs
VINPOFFSET

Input offset including reference ladder error

.. .. .. mV
VHYST

Optional hysteresis

.. .. .. mV
tSTARTUP

Startup time for LPCOMP

.. .. .. µs

This document was last updated on
2019-12-09.
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