DCNF — Domain configuration

The domain configuration (DCNF) module provides a way to identify the CPU by its CPU ID in the device (CPUID). It also provides protection of the AHB multilayer interconnect (AMLI).

To provide for the AMLI protection, the DCNF contains configuration registers that can be used to block some paths from the AHB masters to their respective AHB slaves in the AMLI.

For an illustration of how the AHB masters and slaves are connected through the AMLI, see Memory.

Protection

The DCNF protection involves blocking of paths from AHB masters in an external core to the AHB slaves in the local core's AMLI. This way, the local core's internal resources can be blocked from being accessed by an external core. A set of configuration registers is used to control this behavior.

See Memory to get an overview of the AMLI.

The DCNF configuration registers that enable the DCNF protection are the following:

EXTPERI[n].PROTECT
EXTRAM[n].PROTECT
EXTCODE[n].PROTECT

An attempt to access the blocked resources will trigger a BusFault or a HardFault exception, depending on the value of the BUSFAULTENA bit in the Arm® Cortex®-M33 SHCSR (system handler control and state register), described in the Arm® Cortex®-M33 Devices Generic User Guide.

RAM protection

The protection of RAM regions is configured through the SLAVE-bits of the corresponding master ports' register EXTRAM[n].PROTECT.

Peripheral protection

The protection of peripheral memory regions is configured through the SLAVE-bits of the corresponding master ports' register EXTPERI[n].PROTECT.

Code protection

The protection of code memory regions is configured through the SLAVE-bits of the corresponding master ports' register EXTCODE[0].PROTECT.

Registers

Table 1. Instances
Base address	Domain	Peripheral	Instance	Secure mapping	DMA security	Description	Configuration
0x50000000 0x40000000	APPLICATION	DCNF	DCNF : S DCNF : NS	US	NA	Domain configuration	CPUID value is 0x00000000
0x41000000	NETWORK	DCNF	DCNF	NS	NA	Domain configuration	Registers EXTPERI[n].PROTECT, EXTRAM[n].PROTECT, and EXTCODE[n].PROTECT not available for the network core. CPUID value is 0x00000001

Table 2. Register overview
Register	Offset	Description
CPUID	0x420	CPU ID of this subsystem
EXTPERI[n].PROTECT	0x440	Control access for master connected to AMLI master port EXTPERI[n]
EXTRAM[n].PROTECT	0x460	Control access from master connected to AMLI master port EXTRAM[n]
EXTCODE[n].PROTECT	0x480	Control access from master connected to AMLI master port EXTCODE[n]

CPUID

Address offset: 0x420

CPU ID of this subsystem

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CPUID										CPU ID

EXTPERI[n].PROTECT (n=0..0)

Address offset: 0x440 + (n × 0x4)

Control access for master connected to AMLI master port EXTPERI[n]

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-A	RW	SLAVE[i] (i=0..0)										Control access to slave i of master EXTPERI[n]
			Allowed	0								Access to slave is allowed
			Blocked	1								Access to slave is blocked

EXTRAM[n].PROTECT (n=0..0)

Address offset: 0x460 + (n × 0x4)

Control access from master connected to AMLI master port EXTRAM[n]

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW	SLAVE[i] (i=0..7)										Control access to slave i of master EXTRAM[n]
			Allowed	0								Access to slave is allowed
			Blocked	1								Access to slave is blocked

EXTCODE[n].PROTECT (n=0..0)

Address offset: 0x480 + (n × 0x4)

Control access from master connected to AMLI master port EXTCODE[n]

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-A	RW	SLAVE[i] (i=0..0)										Control access to slave i of master EXTCODE[n]
			Allowed	0								Access to slave is allowed
			Blocked	1								Access to slave is blocked