CTI - Cross Trigger Interface

Configuration interface for the Cross Trigger Interface

Please refer to the CTI section for more information about how to configure the Cross Trigger Interface.

Registers

Table 1. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration
0xE0042000 APPLICATION CTI CTI S NA

Cross-trigger interface

Application core CTI

 
0xE0042000 NETWORK CTI CTI NS NA

Cross-trigger interface

Network core CTI

 
Table 2. Register overview
Register Offset Security Description
CTICONTROL 0x000  

CTI Control register

 
CTIINTACK 0x010  

CTI Interrupt Acknowledge register

 
CTIAPPSET 0x014  

CTI Application Trigger Set register

 
CTIAPPCLEAR 0x018  

CTI Application Trigger Clear register

 
CTIAPPPULSE 0x01C  

CTI Application Pulse register

 
CTIINEN[n] 0x020  

CTI Trigger to Channel Enable register

 
CTIOUTEN[n] 0x0A0  

CTI Channel to Trigger Enable register

 
CTITRIGINSTATUS 0x130  

CTI Trigger In Status register

 
CTITRIGOUTSTATUS 0x134  

CTI Trigger Out Status register

 
CTICHINSTATUS 0x138  

CTI Channel In Status register

 
CTIGATE 0x140  

Enable CTI Channel Gate register

 
DEVARCH 0xFBC  

Device Architecture register

 
DEVID 0xFC8  

Device Configuration register

 
DEVTYPE 0xFCC  

Device Type Identifier register

 
PIDR4 0xFD0  

Peripheral ID4 Register

 
PIDR5 0xFD4  

Peripheral ID5 register

 
PIDR6 0xFD8  

Peripheral ID6 register

 
PIDR7 0xFDC  

Peripheral ID7 register

 
PIDR0 0xFE0  

Peripheral ID0 Register

 
PIDR1 0xFE4  

Peripheral ID1 Register

 
PIDR2 0xFE8  

Peripheral ID2 Register

 
PIDR3 0xFEC  

Peripheral ID3 Register

 
CIDR0 0xFF0  

Component ID0 Register

 
CIDR1 0xFF4  

Component ID1 Register

 
CIDR2 0xFF8  

Component ID2 Register

 
CIDR3 0xFFC  

Component ID3 Register

 

CTICONTROL

Address offset: 0x000

CTI Control register

The CTICONTROL register enables the CTI.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

GLBEN

   

Enables or disables the CTI

     

Disabled

0

All cross-triggering mapping logic functionality is disabled.

     

Enabled

1

Cross-triggering mapping logic functionality is enabled.

CTIINTACK

Address offset: 0x010

CTI Interrupt Acknowledge register

The CTIINTACK register is a software acknowledge for a trigger output. This register is used when ctitrigout is used as a sticky output. That is, no hardware acknowledge is available and software acknowledge is required.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H W

INTACK[i] (i=0..7)

   

Acknowledges the ctitrigout i output.

     

Acknowledge

1

Clears the ctitrigout

CTIAPPSET

Address offset: 0x014

CTI Application Trigger Set register

Writing to the CTIAPPSET register causes a channel event to be raised, corresponding to the bit written to.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D RW

APPSET[i] (i=0..3)

   

Application trigger event for channel i

     

Inactive

0

Application trigger i is inactive.

     

Active

1

Application trigger i is active.

     

Activate

1

Generate channel event for channel i.

CTIAPPCLEAR

Address offset: 0x018

CTI Application Trigger Clear register

Writing to a bit in the CTIAPPCLEAR register clears the corresponding channel event.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D W

APPCLEAR[i] (i=0..3)

   

Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.

     

Clear

1

Clears the event for channel i

CTIAPPPULSE

Address offset: 0x01C

CTI Application Pulse register

A write to this register causes a channel event pulse, one cticlk period, to be generated, corresponding to the bit written to. The pulse external to the CTI can be extended to multi-cycle by the handshaking interface circuits. This register clears itself immediately, so it can be repeatedly written to without software having to clear it.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D W

APPULSE[i] (i=0..3)

   

Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.

     

Generate

1

Generates an event pulse on channel i

CTIINEN[n] (n=0..7)

Address offset: 0x020 + (n × 0x4)

CTI Trigger to Channel Enable register

The CTIINENn register enables the signaling of an event on CTM channels when a trigger event is received by the CTI. There is a bit for each of the four channels implemented. This register does not affect the application trigger operations.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D RW

TRIGINEN[i] (i=0..3)

   

Enables a cross trigger event to channel i when a ctitrigin input is activated

     

Disabled

0

Input trigger n events are ignored by channel i

     

Enabled

1

When an event is received on input trigger n (ctitrigin[n]) generate an event on channel i

CTIOUTEN[n] (n=0..7)

Address offset: 0x0A0 + (n × 0x4)

CTI Channel to Trigger Enable register

The CTIOUTENn register defines which channels can generate a ctitrigout[n] output. There is a bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D RW

TRIGOUTEN[i] (i=0..3)

   

Enables a cross trigger event to ctitrigout when channel i when is activated

     

Disabled

0

Channel i is ignored by output trigger n

     

Enabled

1

When an event occur on channel i, generate an event on output event n (ctitrigout[n])

CTITRIGINSTATUS

Address offset: 0x130

CTI Trigger In Status register

The CTITRIGINSTATUS register provides the status of the ctitrigin inputs.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H R

TRIGINSTATUS[i] (i=0..7)

   

Shows the status of ctitrigini input

     

Active

1

Ctitrigin i is active

     

Inactive

0

Ctitrigin i is inactive

CTITRIGOUTSTATUS

Address offset: 0x134

CTI Trigger Out Status register

The CTITRIGOUTSTATUS register provides the status of the ctitrigout outputs.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H R

TRIGOUTSTATUS[i] (i=0..7)

   

Shows the status of ctitrigouti output

     

Active

1

Ctitrigout i is active

     

Inactive

0

Ctitrigout i is inactive

CTICHINSTATUS

Address offset: 0x138

CTI Channel In Status register

The CTICHINSTATUS register provides the status of the ctichin inputs.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D R

CTICHINSTATUS[i] (i=0..3)

   

Shows the status of the ctitrigin i input.

     

Active

1

Ctichin i is active

     

Inactive

0

Ctichin i is inactive

CTIGATE

Address offset: 0x140

Enable CTI Channel Gate register

The CTIGATE register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs. It can be used effectively with CTIAPPSET, CTIAPPCLEAR, and CTIAPPPULSE for asserting trigger outputs by asserting channels, without affecting the rest of the system. On reset, this register is 0xF, and channel propagation is enabled.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        

D

C

B

A

Reset 0x0000000F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
ID Access Field Value ID Value Description
A-D RW

CTIGATEEN[i] (i=0..3)

   

Enable ctichouti

     

Enabled

1

Enable ctichout channel i propagation

     

Disabled

0

Disable ctichout channel i propagation

DEVARCH

Address offset: 0xFBC

Device Architecture register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x47701A14 0 1 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 0
ID Access Field Value ID Value Description
A R

Architecture

   

Contains the CTI device architecture

DEVID

Address offset: 0xFC8

Device Configuration register

The DEVID register indicates the capabilities of the component.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                        

C

C

C

C

B

B

B

B

B

B

B

B

     

A

A

A

A

A

Reset 0x00040800 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

EXTMUXNUM

   

Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present.

B R

NUMTRIG

   

Number of ECT triggers available

C R

NUMCH

   

Number of ECT channels available

DEVTYPE

Address offset: 0xFCC

Device Type Identifier register

The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

B

B

B

B

A

A

A

A

Reset 0x00000014 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
ID Access Field Value ID Value Description
A R

MAJOR

   

Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component

     

Controller

0b0100

Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system

B R

SUB

   

Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field.

     

Crosstrigger

0b0001

Indicates that this component is a sub-triggering component

PIDR4

Address offset: 0xFD0

Peripheral ID4 Register

The PIDR4 register is part of the set of peripheral identification registers. Contains part of the designer identity and the memory size.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

B

B

B

B

A

A

A

A

Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ID Access Field Value ID Value Description
A R

DES_2

   

Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component

     

Code

0b0100

JEDEC continuation code

B R

SIZE

   

Always 0b0000. Indicates that the device only occupies 4KB of memory

PIDR5

Address offset: 0xFD4

Peripheral ID5 register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
 

PIDR6

Address offset: 0xFD8

Peripheral ID6 register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
 

PIDR7

Address offset: 0xFDC

Peripheral ID7 register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
 

PIDR0

Address offset: 0xFE0

Peripheral ID0 Register

The PIDR0 register is part of the set of peripheral identification registers. Contains part of the designer- specific part number.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

A

A

A

A

A

A

A

A

Reset 0x00000021 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
ID Access Field Value ID Value Description
A R

PART_0

   

Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number

     

PartnumberL

0x21

Indicates bits[7:0] of the part number of the component

PIDR1

Address offset: 0xFE4

Peripheral ID1 Register

The PIDR1 register is part of the set of peripheral identification registers. Contains part of the designer- specific part number and part of the designer identity

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

B

B

B

B

A

A

A

A

Reset 0x000000BD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1
ID Access Field Value ID Value Description
A R

PART_1

   

Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number

     

PartnumberH

0b1101

Indicates bits[11:8] of the part number of the component

B R

DES_0

   

Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component

     

Arm

0b1011

ARM. Bits[3:0] of the JEDEC JEP106 Identity Code

PIDR2

Address offset: 0xFE8

Peripheral ID2 Register

The PIDR2 register is part of the set of peripheral identification registers. Contains part of the designer identity and the product revision.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

C

C

C

C

B

A

A

A

Reset 0x0000000B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
ID Access Field Value ID Value Description
A R

DES_1

   

Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component

     

Arm

0b011

ARM. Bits[6:4] of the JEDEC JEP106 Identity Code

B R

JEDEC

   

Always 1. Indicates that the JEDEC-assigned designer ID is used

C R

REVISION

   

Peripheral revision

     

Rev0p0

0b0000

This device is at r0p0

PIDR3

Address offset: 0xFEC

Peripheral ID3 Register

The PIDR3 register is part of the set of peripheral identification registers. Contains the REVAND and CMOD fields.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

B

B

B

B

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

CMOD

   

Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component.

     

Unmodified

0b000

Indicates that the customer has not modified this component

B R

REVAND

   

Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000.

     

NoErrata

0b000

Indicates that there are no errata fixes to this component

CIDR0

Address offset: 0xFF0

Component ID0 Register

The CIDR0 register is a component identification register that indicates the presence of identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

A

A

A

A

A

A

A

A

Reset 0x0000000D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
ID Access Field Value ID Value Description
A R

PRMBL_0

   

Preamble[0]. Contains bits[7:0] of the component identification code

     

Value

0x0D

Bits[7:0] of the identification code

CIDR1

Address offset: 0xFF4

Component ID1 Register

The CIDR1 register is a component identification register that indicates the presence of identification registers. This register also indicates the component class.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

B

B

B

B

A

A

A

A

Reset 0x00000090 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0
ID Access Field Value ID Value Description
A R

PRMBL_1

   

Preamble[1]. Contains bits[11:8] of the component identification code

     

Value

0b0000

Bits[11:8] of the identification code

B R

CLASS

   

Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code

     

Coresight

0b1001

Indicates that the component is a CoreSight component

CIDR2

Address offset: 0xFF8

Component ID2 Register

The CIDR2 register is a component identification register that indicates the presence of identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

A

A

A

A

A

A

A

A

Reset 0x00000005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
ID Access Field Value ID Value Description
A R

PRMBL_2

   

Preamble[2]. Contains bits[23:16] of the component identification code

     

Value

0x05

Bits[23:16] of the identification code

CIDR3

Address offset: 0xFFC

Component ID3 Register

The CIDR3 register is a component identification register that indicates the presence of identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                

A

A

A

A

A

A

A

A

Reset 0x000000B1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1
ID Access Field Value ID Value Description
A R

PRMBL_3

   

Preamble[3]. Contains bits[31:24] of the component identification code

     

Value

0xB1

Bits[31:24] of the identification code


This document was last updated on
2019-12-09.
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