Memory

The application microcontroller has embedded 1024 kB flash and 256 kB RAM for application code and data storage.

As illustrated in Memory layout, both CPU and EasyDMA are able to access RAM via the AHB multilayer interconnect. See AHB multilayer interconnect and EasyDMA for more information about AHB multilayer interconnect and EasyDMA respectively. The LTE modem can access all application MCU memory, but typically a small portion of RAM is dedicated to data exchange between application MCU and the modem baseband controller.

Figure 1. Memory layout
Memory layout

RAM - Random access memory

RAM can be read and written an unlimited number of times by the CPU and the EasyDMA.

Each RAM AHB slave is connected to one or more RAM sections. See Memory layout for more information.

The RAM blocks power states and retention states in System ON and System OFF modes are controlled by the VMC.

Flash - Non-volatile memory

Flash can be read an unlimited number of times by the CPU and is accessible via the AHB interface connected to the CPU, see Memory layout for more information. There are restrictions on the number of times flash can be written and erased, and also on how it can be written. Writing to flash is managed by the non-volatile memory controller (NVMC).

Memory map

All memory and registers are found in the same address space, as illustrated in the device memory map below.

Figure 2. Memory map
Memory map

Some of the registers are retained (their values kept). Read more about retained registers in Retained registers and Reset behavior.

Instantiation

Table 1. Instantiation table
ID Base address Peripheral Instance Secure mapping DMA security Description
3 0x50003000 SPU SPU S NA

System Protection Unit

 
4

0x50004000
0x40004000

REGULATORS

REGULATORS : S
REGULATORS : NS

US

NA

Regulator configuration

 
5

0x50005000
0x40005000

CLOCK

CLOCK : S
CLOCK : NS

US

NA

Clock control

 
5

0x50005000
0x40005000

POWER

POWER : S
POWER : NS

US

NA

Power control

 
6 0x50006000 CTRLAPPERI CTRL_AP_PERI S NA

CTRL-AP-PERI

 
8

0x50008000
0x40008000

SPIM

SPIM0 : S
SPIM0 : NS

US

SA

SPI master 0

 
8

0x50008000
0x40008000

SPIS

SPIS0 : S
SPIS0 : NS

US

SA

SPI slave 0

 
8

0x50008000
0x40008000

TWIM

TWIM0 : S
TWIM0 : NS

US

SA

Two-wire interface master 0

 
8

0x50008000
0x40008000

TWIS

TWIS0 : S
TWIS0 : NS

US

SA

Two-wire interface slave 0

 
8

0x50008000
0x40008000

UARTE

UARTE0 : S
UARTE0 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 0

 
9

0x50009000
0x40009000

SPIM

SPIM1 : S
SPIM1 : NS

US

SA

SPI master 1

 
9

0x50009000
0x40009000

SPIS

SPIS1 : S
SPIS1 : NS

US

SA

SPI slave 1

 
9

0x50009000
0x40009000

TWIM

TWIM1 : S
TWIM1 : NS

US

SA

Two-wire interface master 1

 
9

0x50009000
0x40009000

TWIS

TWIS1 : S
TWIS1 : NS

US

SA

Two-wire interface slave 1

 
9

0x50009000
0x40009000

UARTE

UARTE1 : S
UARTE1 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 1

 
10

0x5000A000
0x4000A000

SPIM

SPIM2 : S
SPIM2 : NS

US

SA

SPI master 2

 
10

0x5000A000
0x4000A000

SPIS

SPIS2 : S
SPIS2 : NS

US

SA

SPI slave 2

 
10

0x5000A000
0x4000A000

TWIM

TWIM2 : S
TWIM2 : NS

US

SA

Two-wire interface master 2

 
10

0x5000A000
0x4000A000

TWIS

TWIS2 : S
TWIS2 : NS

US

SA

Two-wire interface slave 2

 
10

0x5000A000
0x4000A000

UARTE

UARTE2 : S
UARTE2 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 2

 
11

0x5000B000
0x4000B000

SPIM

SPIM3 : S
SPIM3 : NS

US

SA

SPI master 3

 
11

0x5000B000
0x4000B000

SPIS

SPIS3 : S
SPIS3 : NS

US

SA

SPI slave 3

 
11

0x5000B000
0x4000B000

TWIM

TWIM3 : S
TWIM3 : NS

US

SA

Two-wire interface master 3

 
11

0x5000B000
0x4000B000

TWIS

TWIS3 : S
TWIS3 : NS

US

SA

Two-wire interface slave 3

 
11

0x5000B000
0x4000B000

UARTE

UARTE3 : S
UARTE3 : NS

US

SA

Universal asynchronous receiver/transmitter with EasyDMA 3

 
13 0x5000D000 GPIOTE GPIOTE0 S NA

Secure GPIO tasks and events

 
14

0x5000E000
0x4000E000

SAADC

SAADC : S
SAADC : NS

US

SA

Analog to digital converter

 
15

0x5000F000
0x4000F000

TIMER

TIMER0 : S
TIMER0 : NS

US

NA

Timer 0

 
16

0x50010000
0x40010000

TIMER

TIMER1 : S
TIMER1 : NS

US

NA

Timer 1

 
17

0x50011000
0x40011000

TIMER

TIMER2 : S
TIMER2 : NS

US

NA

Timer 2

 
20

0x50014000
0x40014000

RTC

RTC0 : S
RTC0 : NS

US

NA

Real time counter 0

 
21

0x50015000
0x40015000

RTC

RTC1 : S
RTC1 : NS

US

NA

Real time counter 1

 
23

0x50017000
0x40017000

DPPIC

DPPIC : S
DPPIC : NS

SPLIT

NA

DPPI configuration

 
24

0x50018000
0x40018000

WDT

WDT : S
WDT : NS

US

NA

Watchdog timer

 
27

0x5001B000
0x4001B000

EGU

EGU0 : S
EGU0 : NS

US

NA

Event generator unit 0

 
28

0x5001C000
0x4001C000

EGU

EGU1 : S
EGU1 : NS

US

NA

Event generator unit 1

 
29

0x5001D000
0x4001D000

EGU

EGU2 : S
EGU2 : NS

US

NA

Event generator unit 2

 
30

0x5001E000
0x4001E000

EGU

EGU3 : S
EGU3 : NS

US

NA

Event generator unit 3

 
31

0x5001F000
0x4001F000

EGU

EGU4 : S
EGU4 : NS

US

NA

Event generator unit 4

 
32

0x50020000
0x40020000

EGU

EGU5 : S
EGU5 : NS

US

NA

Event generator unit 5

 
33

0x50021000
0x40021000

PWM

PWM0 : S
PWM0 : NS

US

SA

Pulse width modulation unit 0

 
34

0x50022000
0x40022000

PWM

PWM1 : S
PWM1 : NS

US

SA

Pulse width modulation unit 1

 
35

0x50023000
0x40023000

PWM

PWM2 : S
PWM2 : NS

US

SA

Pulse width modulation unit 2

 
36

0x50024000
0x40024000

PWM

PWM3 : S
PWM3 : NS

US

SA

Pulse width modulation unit 3

 
38

0x50026000
0x40026000

PDM

PDM : S
PDM : NS

US

SA

Pulse density modulation (digital microphone) interface

 
40

0x50028000
0x40028000

I2S

I2S : S
I2S : NS

US

SA

Inter-IC Sound

 
42

0x5002A000
0x4002A000

IPC

IPC : S
IPC : NS

US

NA

Interprocessor communication

 
44

0x5002C000
0x4002C000

FPU

FPU : S
FPU : NS

US

NA

Floating-point unit

 
49 0x40031000 GPIOTE GPIOTE1 NS NA

Non Secure GPIO tasks and events

 
57

0x50039000
0x40039000

KMU

KMU : S
KMU : NS

SPLIT

NA

Key management unit

 
57

0x50039000
0x40039000

NVMC

NVMC : S
NVMC : NS

SPLIT

NA

Non-volatile memory controller

 
58

0x5003A000
0x4003A000

VMC

VMC : S
VMC : NS

US

NA

Volatile memory controller

 
64 0x50840000 CC_HOST_RGF CC_HOST_RGF S NSA

Host platform interface

 
64 0x50840000 CRYPTOCELL CRYPTOCELL S NSA

CryptoCell sub-system control interface

 
66

0x50842500
0x40842500

GPIO

P0 : S
P0 : NS

SPLIT

NA

General purpose input and output

 
N/A 0x00FF0000 FICR FICR S NA

Factory information configuration

 
N/A 0x00FF8000 UICR UICR S NA

User information configuration

 
N/A 0xE0080000 TAD TAD S NA

Trace and debug control

 
 

Peripheral access control capabilities

Information about the peripheral access control capabilities can be found in the instantiation table.

The instantiation table has two columns containing the information about access control capabilities for a peripheral:

  • Secure mapping: This column defines configuration capabilities for TrustZone®-M secure attribute.
  • DMA security: This column indicates if the peripheral has DMA capabilities, and if DMA transfer can be assigned to a different security attribute than the peripheral itself.

For details on options in secure mapping column and DMA security column, see the following tables respecitvely.

Table 2. Secure mapping column options
Abbreviation Description
NS Non-secure: This peripheral is always accessible as a non-secure peripheral.
S Secure: This peripheral is always accessible as a secure peripheral.
US User-selectable: Non-secure or secure attribute for this peripheral is defined by the PERIPHID[0].PERM register.
SPLIT Both non-secure and secure: The same resource is shared by both secure and non-secure code.
Table 3. DMA security column options
Abbreviation Description
NA Not applicable: Peripheral has no DMA capability.
NSA No separate attribute: Peripheral has DMA, and DMA transfers always have the same security attribute as assigned to the peripheral.
SA Separate attribute: Peripheral has DMA, and DMA transfers can have a different security attribute than the one assigned to the peripheral.