CLOCK — Clock control

The CLOCK module provides one of the interfaces to power and clock management configuration settings.

Through CLOCK module it is able to configure the following:
  • LFCLK clock source setup
  • LFCLK and HFCLK status
  • Tasks and events
  • Interrupts
  • Reset
Note: Registers INTEN, INTENSET, and INTENCLR are the same registers (at the same address) as corresponding registers in POWER — Power control.

Registers

Table 1. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x50005000
0x40005000

CLOCK

CLOCK : S
CLOCK : NS

US

NA

Clock control

   
Table 2. Register overview
Register Offset Security Description
TASKS_HFCLKSTART 0x000  

Start HFCLK source

 
TASKS_HFCLKSTOP 0x004  

Stop HFCLK source

 
TASKS_LFCLKSTART 0x008  

Start LFCLK source

 
TASKS_LFCLKSTOP 0x00C  

Stop LFCLK source

 
SUBSCRIBE_HFCLKSTART 0x080  

Subscribe configuration for task HFCLKSTART

 
SUBSCRIBE_HFCLKSTOP 0x084  

Subscribe configuration for task HFCLKSTOP

 
SUBSCRIBE_LFCLKSTART 0x088  

Subscribe configuration for task LFCLKSTART

 
SUBSCRIBE_LFCLKSTOP 0x08C  

Subscribe configuration for task LFCLKSTOP

 
EVENTS_HFCLKSTARTED 0x100  

HFCLK oscillator started

 
EVENTS_LFCLKSTARTED 0x104  

LFCLK started

 
PUBLISH_HFCLKSTARTED 0x180  

Publish configuration for event HFCLKSTARTED

 
PUBLISH_LFCLKSTARTED 0x184  

Publish configuration for event LFCLKSTARTED

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
INTPEND 0x30C  

Pending interrupts

 
HFCLKRUN 0x408  

Status indicating that HFCLKSTART task has been triggered

 
HFCLKSTAT 0x40C  

The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)

 
LFCLKRUN 0x414  

Status indicating that LFCLKSTART task has been triggered

 
LFCLKSTAT 0x418  

The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)

 
LFCLKSRCCOPY 0x41C  

Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered

 
LFCLKSRC 0x518  

Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register.

 

TASKS_HFCLKSTART

Address offset: 0x000

Start HFCLK source

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_HFCLKSTART

   

Start HFCLK source

     

Trigger

1

Trigger task

TASKS_HFCLKSTOP

Address offset: 0x004

Stop HFCLK source

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_HFCLKSTOP

   

Stop HFCLK source

     

Trigger

1

Trigger task

TASKS_LFCLKSTART

Address offset: 0x008

Start LFCLK source

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_LFCLKSTART

   

Start LFCLK source

     

Trigger

1

Trigger task

TASKS_LFCLKSTOP

Address offset: 0x00C

Stop LFCLK source

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_LFCLKSTOP

   

Stop LFCLK source

     

Trigger

1

Trigger task

SUBSCRIBE_HFCLKSTART

Address offset: 0x080

Subscribe configuration for task HFCLKSTART

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task HFCLKSTART will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_HFCLKSTOP

Address offset: 0x084

Subscribe configuration for task HFCLKSTOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task HFCLKSTOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_LFCLKSTART

Address offset: 0x088

Subscribe configuration for task LFCLKSTART

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task LFCLKSTART will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_LFCLKSTOP

Address offset: 0x08C

Subscribe configuration for task LFCLKSTOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task LFCLKSTOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_HFCLKSTARTED

Address offset: 0x100

HFCLK oscillator started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_HFCLKSTARTED

   

HFCLK oscillator started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_LFCLKSTARTED

Address offset: 0x104

LFCLK started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_LFCLKSTARTED

   

LFCLK started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_HFCLKSTARTED

Address offset: 0x180

Publish configuration for event HFCLKSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event HFCLKSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_LFCLKSTARTED

Address offset: 0x184

Publish configuration for event LFCLKSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event LFCLKSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

HFCLKSTARTED

   

Enable or disable interrupt for event HFCLKSTARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

LFCLKSTARTED

   

Enable or disable interrupt for event LFCLKSTARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

HFCLKSTARTED

   

Write '1' to enable interrupt for event HFCLKSTARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

LFCLKSTARTED

   

Write '1' to enable interrupt for event LFCLKSTARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

HFCLKSTARTED

   

Write '1' to disable interrupt for event HFCLKSTARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

LFCLKSTARTED

   

Write '1' to disable interrupt for event LFCLKSTARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

HFCLKSTARTED

   

Read pending status of interrupt for event HFCLKSTARTED

     

NotPending

0

Read: Not pending

     

Pending

1

Read: Pending

B R

LFCLKSTARTED

   

Read pending status of interrupt for event LFCLKSTARTED

     

NotPending

0

Read: Not pending

     

Pending

1

Read: Pending

HFCLKRUN

Address offset: 0x408

Status indicating that HFCLKSTART task has been triggered

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

STATUS

   

HFCLKSTART task triggered or not

     

NotTriggered

0

Task not triggered

     

Triggered

1

Task triggered

HFCLKSTAT

Address offset: 0x40C

The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                               B                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

SRC

   

Active clock source

     

HFXO

1

HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator

B R

STATE

   

HFCLK state

     

NotRunning

0

HFXO has not been started or HFCLKSTOP task has been triggered

     

Running

1

HFXO has been started (HFCLKSTARTED event has been generated)

LFCLKRUN

Address offset: 0x414

Status indicating that LFCLKSTART task has been triggered

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

STATUS

   

LFCLKSTART task triggered or not

     

NotTriggered

0

Task not triggered

     

Triggered

1

Task triggered

LFCLKSTAT

Address offset: 0x418

The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                               B                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

SRC

   

Active clock source

     

RFU

0

Reserved for future use

     

LFRC

1

32.768 kHz RC oscillator

     

LFXO

2

32.768 kHz crystal oscillator

B R

STATE

   

LFCLK state

     

NotRunning

0

Requested LFCLK source has not been started or LFCLKSTOP task has been triggered

     

Running

1

Requested LFCLK source has been started (LFCLKSTARTED event has been generated)

LFCLKSRCCOPY

Address offset: 0x41C

Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A R

SRC

   

Clock source

     

RFU

0

Reserved for future use

     

LFRC

1

32.768 kHz RC oscillator

     

LFXO

2

32.768 kHz crystal oscillator

LFCLKSRC

Address offset: 0x518

Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A RW

SRC

   

Clock source

     

RFU

0

Reserved for future use (equals selecting LFRC)

     

LFRC

1

32.768 kHz RC oscillator

     

LFXO

2

32.768 kHz crystal oscillator