TIMER — Timer/counter

This peripheral is a general purpose timer designed to keep track of time in user-selective time intervals, it can operate in two modes: timer and counter.

Figure 1. Block schematic for timer/counter

The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler that can divide the timer input clock from the HFCLK controller. Clock source selection between PCLK16M and PCLK1M is automatic according to TIMER base frequency set by the prescaler. The TIMER base frequency is always given as 16 MHz divided by the prescaler value.

The PPI system allows a TIMER event to trigger a task of any other system peripheral of the device. The PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels.

The TIMER can operate in two modes, Timer mode and Counter mode. In both modes, the TIMER is started by triggering the START task, and stopped by triggering the STOP task. After the timer is stopped the timer can resume timing/counting by triggering the START task again. When timing/counting is resumed, the timer will continue from the value it had prior to being stopped.

In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer frequency fTIMER as illustrated in Block schematic for timer/counter. The timer frequency is derived from PCLK16M as shown below, using the values specified in the PRESCALER register:


    fTIMER = 16 MHz / (2PRESCALER)
    

When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.

In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the COUNT task has no effect in Timer mode.

The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE register.

PRESCALER and the BITMODE must only be updated when the timer is stopped. If these registers are updated while the TIMER is started then this may result in unpredictable behavior.

When the timer is incremented beyond its maximum value the Counter register will overflow and the TIMER will automatically start over from zero.

The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR task.

The TIMER implements multiple capture/compare registers.

Independent of prescaler setting the accuracy of the TIMER is equivalent to one tick of the timer frequency fTIMER as illustrated in Block schematic for timer/counter.

Capture

The TIMER implements one capture task for every available capture/compare register.

Every time the CAPTURE[n] task is triggered, the Counter value is copied to the CC[n] register.

Compare

The TIMER implements one COMPARE event for every available capture/compare register.

A COMPARE event is generated when the Counter is incremented and then becomes equal to the value specified in one of the capture compare registers. When the Counter value becomes equal to the value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is generated.

BITMODE specifies how many bits of the Counter register and the capture/compare register that are used when the comparison is performed. Other bits will be ignored.

The COMPARE event can be configured to operate in one-shot mode by configuring the corresponding ONESHOTEN[n] register. COMPARE[n] event is generated the first time the Counter matches CC[n] after CC[n] has been written.

Task delays

After the TIMER is started, the CLEAR task, COUNT task and the STOP task will guarantee to take effect within one clock cycle of the PCLK16M.

Task priority

If the START task and the STOP task are triggered at the same time, that is, within the same period of PCLK16M, the STOP task will be prioritized.

If one or more of the CAPTURE tasks and the CLEAR task is triggered at the same time, that is, within the same period of PCLK16M, the CLEAR task will be prioritized. This means that the CC register for the relevant CAPTURE task will be set to 0.

Registers

Table 1. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x5000F000
0x4000F000

TIMER

TIMER0 : S
TIMER0 : NS

US

NA

Timer 0

   

0x50010000
0x40010000

TIMER

TIMER1 : S
TIMER1 : NS

US

NA

Timer 1

   

0x50011000
0x40011000

TIMER

TIMER2 : S
TIMER2 : NS

US

NA

Timer 2

   
Table 2. Register overview
Register Offset Security Description
TASKS_START 0x000  

Start Timer

 
TASKS_STOP 0x004  

Stop Timer

 
TASKS_COUNT 0x008  

Increment Timer (Counter mode only)

 
TASKS_CLEAR 0x00C  

Clear time

 
TASKS_SHUTDOWN 0x010  

Shut down timer

Deprecated

TASKS_CAPTURE[0] 0x040  

Capture Timer value to CC[0] register

 
TASKS_CAPTURE[1] 0x044  

Capture Timer value to CC[1] register

 
TASKS_CAPTURE[2] 0x048  

Capture Timer value to CC[2] register

 
TASKS_CAPTURE[3] 0x04C  

Capture Timer value to CC[3] register

 
TASKS_CAPTURE[4] 0x050  

Capture Timer value to CC[4] register

 
TASKS_CAPTURE[5] 0x054  

Capture Timer value to CC[5] register

 
SUBSCRIBE_START 0x080  

Subscribe configuration for task START

 
SUBSCRIBE_STOP 0x084  

Subscribe configuration for task STOP

 
SUBSCRIBE_COUNT 0x088  

Subscribe configuration for task COUNT

 
SUBSCRIBE_CLEAR 0x08C  

Subscribe configuration for task CLEAR

 
SUBSCRIBE_SHUTDOWN 0x090  

Subscribe configuration for task SHUTDOWN

Deprecated

SUBSCRIBE_CAPTURE[0] 0x0C0  

Subscribe configuration for task CAPTURE[0]

 
SUBSCRIBE_CAPTURE[1] 0x0C4  

Subscribe configuration for task CAPTURE[1]

 
SUBSCRIBE_CAPTURE[2] 0x0C8  

Subscribe configuration for task CAPTURE[2]

 
SUBSCRIBE_CAPTURE[3] 0x0CC  

Subscribe configuration for task CAPTURE[3]

 
SUBSCRIBE_CAPTURE[4] 0x0D0  

Subscribe configuration for task CAPTURE[4]

 
SUBSCRIBE_CAPTURE[5] 0x0D4  

Subscribe configuration for task CAPTURE[5]

 
EVENTS_COMPARE[0] 0x140  

Compare event on CC[0] match

 
EVENTS_COMPARE[1] 0x144  

Compare event on CC[1] match

 
EVENTS_COMPARE[2] 0x148  

Compare event on CC[2] match

 
EVENTS_COMPARE[3] 0x14C  

Compare event on CC[3] match

 
EVENTS_COMPARE[4] 0x150  

Compare event on CC[4] match

 
EVENTS_COMPARE[5] 0x154  

Compare event on CC[5] match

 
PUBLISH_COMPARE[0] 0x1C0  

Publish configuration for event COMPARE[0]

 
PUBLISH_COMPARE[1] 0x1C4  

Publish configuration for event COMPARE[1]

 
PUBLISH_COMPARE[2] 0x1C8  

Publish configuration for event COMPARE[2]

 
PUBLISH_COMPARE[3] 0x1CC  

Publish configuration for event COMPARE[3]

 
PUBLISH_COMPARE[4] 0x1D0  

Publish configuration for event COMPARE[4]

 
PUBLISH_COMPARE[5] 0x1D4  

Publish configuration for event COMPARE[5]

 
SHORTS 0x200  

Shortcuts between local events and tasks

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
MODE 0x504  

Timer mode selection

 
BITMODE 0x508  

Configure the number of bits used by the TIMER

 
PRESCALER 0x510  

Timer prescaler register

 
ONESHOTEN[0] 0x514  

Enable one-shot operation for Capture/Compare channel 0

 
ONESHOTEN[1] 0x518  

Enable one-shot operation for Capture/Compare channel 1

 
ONESHOTEN[2] 0x51C  

Enable one-shot operation for Capture/Compare channel 2

 
ONESHOTEN[3] 0x520  

Enable one-shot operation for Capture/Compare channel 3

 
ONESHOTEN[4] 0x524  

Enable one-shot operation for Capture/Compare channel 4

 
ONESHOTEN[5] 0x528  

Enable one-shot operation for Capture/Compare channel 5

 
CC[0] 0x540  

Capture/Compare register 0

 
CC[1] 0x544  

Capture/Compare register 1

 
CC[2] 0x548  

Capture/Compare register 2

 
CC[3] 0x54C  

Capture/Compare register 3

 
CC[4] 0x550  

Capture/Compare register 4

 
CC[5] 0x554  

Capture/Compare register 5

 

TASKS_START

Address offset: 0x000

Start Timer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_START

   

Start Timer

     

Trigger

1

Trigger task

TASKS_STOP

Address offset: 0x004

Stop Timer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOP

   

Stop Timer

     

Trigger

1

Trigger task

TASKS_COUNT

Address offset: 0x008

Increment Timer (Counter mode only)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_COUNT

   

Increment Timer (Counter mode only)

     

Trigger

1

Trigger task

TASKS_CLEAR

Address offset: 0x00C

Clear time

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_CLEAR

   

Clear time

     

Trigger

1

Trigger task

TASKS_SHUTDOWN ( Deprecated )

Address offset: 0x010

Shut down timer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_SHUTDOWN

   

Shut down timer

Deprecated

     

Trigger

1

Trigger task

TASKS_CAPTURE[n] (n=0..5)

Address offset: 0x040 + (n × 0x4)

Capture Timer value to CC[n] register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_CAPTURE

   

Capture Timer value to CC[n] register

     

Trigger

1

Trigger task

SUBSCRIBE_START

Address offset: 0x080

Subscribe configuration for task START

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task START will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOP

Address offset: 0x084

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task STOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_COUNT

Address offset: 0x088

Subscribe configuration for task COUNT

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task COUNT will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_CLEAR

Address offset: 0x08C

Subscribe configuration for task CLEAR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task CLEAR will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_SHUTDOWN ( Deprecated )

Address offset: 0x090

Subscribe configuration for task SHUTDOWN

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task SHUTDOWN will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_CAPTURE[n] (n=0..5)

Address offset: 0x0C0 + (n × 0x4)

Subscribe configuration for task CAPTURE[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task CAPTURE[n] will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_COMPARE[n] (n=0..5)

Address offset: 0x140 + (n × 0x4)

Compare event on CC[n] match

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_COMPARE

   

Compare event on CC[n] match

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_COMPARE[n] (n=0..5)

Address offset: 0x1C0 + (n × 0x4)

Publish configuration for event COMPARE[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event COMPARE[n] will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                     L K J I H G     F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-F RW

COMPARE[i]_CLEAR (i=0..5)

   

Shortcut between event COMPARE[i] and task CLEAR

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

G-L RW

COMPARE[i]_STOP (i=0..5)

   

Shortcut between event COMPARE[i] and task STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     F E D C B A                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-F RW

COMPARE[i] (i=0..5)

   

Write '1' to enable interrupt for event COMPARE[i]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     F E D C B A                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-F RW

COMPARE[i] (i=0..5)

   

Write '1' to disable interrupt for event COMPARE[i]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

MODE

Address offset: 0x504

Timer mode selection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

MODE

   

Timer mode

     

Timer

0

Select Timer mode

     

Counter

1

Select Counter mode

Deprecated

     

LowPowerCounter

2

Select Low Power Counter mode

BITMODE

Address offset: 0x508

Configure the number of bits used by the TIMER

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

BITMODE

   

Timer bit width

     

16Bit

0

16 bit timer bit width

     

08Bit

1

8 bit timer bit width

     

24Bit

2

24 bit timer bit width

     

32Bit

3

32 bit timer bit width

PRESCALER

Address offset: 0x510

Timer prescaler register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         A A A A
Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ID Access Field Value ID Value Description
A RW

PRESCALER

 

[0..9]

Prescaler value

ONESHOTEN[n] (n=0..5)

Address offset: 0x514 + (n × 0x4)

Enable one-shot operation for Capture/Compare channel n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ONESHOTEN

   

Enable one-shot operation

Configures the corresponding compare-channel for one-shot operation

     

Disable

0

Disable one-shot operation

Compare event is generated every time the Counter matches CC[n]

     

Enable

1

Enable one-shot operation

Compare event is generated the first time the Counter matches CC[n] after CC[n] has been written

CC[n] (n=0..5)

Address offset: 0x540 + (n × 0x4)

Capture/Compare register n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CC

   

Capture/Compare value

Only the number of bits indicated by BITMODE will be used by the TIMER.

Electrical specification