TWIS — I2C compatible two-wire interface slave with EasyDMA

TWI slave with EasyDMA (TWIS) is compatible with I2C operating at 100 kHz and 400 kHz. The TWI transmitter and receiver implement EasyDMA.

Figure 1. TWI slave with EasyDMA
TWI slave with EasyDMA

A typical TWI setup consists of one master and one or more slaves. For an example, see A typical TWI setup comprising one master and three slaves. TWIS is only able to operate with a single master on the TWI bus.

Figure 2. A typical TWI setup comprising one master and three slaves
A typical TWI setup comprising one master and three slaves

The TWI slave state machine is illustrated in TWI slave state machine and TWI slave state machine symbols is explaining the different symbols used in the state machine.

Figure 3. TWI slave state machine
TWI slave state machine

Table 1. TWI slave state machine symbols
Symbol Type Description
ENABLE Register The TWI slave has been enabled via the ENABLE register
PREPARETX Task The TASKS_PREPARETX task has been triggered
STOP Task The TASKS_STOP task has been triggered
PREPARERX Task The TASKS_PREPARERX task has been triggered
STOPPED Event The EVENTS_STOPPED event was generated
RXSTARTED Event The EVENTS_RXSTARTED event was generated
TXSTARTED Event The EVENTS_TXSTARTED event was generated
TX prepared Internal Internal flag indicating that a TASKS_PREPARETX task has been triggered. This flag is not visible to the user.
RX prepared Internal Internal flag indicating that a TASKS_PREPARERX task has been triggered. This flag is not visible to the user.
Unprepare TX Internal Clears the internal 'TX prepared' flag until next TASKS_PREPARETX task.
Unprepare RX Internal Clears the internal 'RX prepared' flag until next TASKS_PREPARERX task.
Stop sequence TWI protocol A TWI stop sequence was detected
Restart sequence TWI protocol A TWI restart sequence was detected

The TWI slave supports clock stretching performed by the master.

The TWI slave operates in a low power mode while waiting for a TWI master to initiate a transfer. As long as the TWI slave is not addressed, it will remain in this low power mode.

To secure correct behaviour of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG and the ADDRESS[n] registers, must be configured prior to enabling the TWI slave through the ENABLE register. Similarly, changing these settings must be performed while the TWI slave is disabled. Failing to do so may result in unpredictable behaviour.

EasyDMA

The TWI slave implements EasyDMA for reading and writing to and from the RAM.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.

TWI slave responding to a read command

Before the TWI slave can respond to a read command the TWI slave must be configured correctly and enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume IIDLE .

A read command is started when the TWI master generates a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.

The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is configured in the ADDRESS registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the read command if the address presented by the master matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ event when it acknowledges the read command.

The TWI slave is only able to detect a read command from the IDLE state.

The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.

When the read command is received the TWI slave will enter the TX state if the internal 'TX prepared' flag is set.

If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch the master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.

The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when it enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the master using the master's clock. The TWI slave will consume ITX in this mode.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the TX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag ('unprepare TX') and go back to the IDLE state when it has stopped.

The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC register to the master instead. If this happens, an ERROR event will be generated.

The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is generated.

The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state when it has stopped, see also Terminating an ongoing TWI transaction.

Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a transaction to see how many bytes were sent.

A typical TWI slave read command response is illustrated in The TWI slave responding to a read command. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave following a SUSPEND task.

Figure 4. The TWI slave responding to a read command
The TWI slave responding to a read command

TWI slave responding to a write command

Before the TWI slave can respond to a write command the TWI slave must be configured correctly and enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume IIDLE.

A write command is started when the TWI master generates a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave.

The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is configured in the ADDRESS registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the write command if the address presented by the master matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE event if it acknowledges the write command.

The TWI slave is only able to detect a write command from the IDLE state.

The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered.

When the write command is received the TWI slave will enter the RX state if the internal 'RX prepared' flag is set.

If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch the master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set.

The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare RX') when it enters the RX state. In this state the TWI slave will be able to receive the bytes sent by the TWI master. The TWI slave will consume IRX in this mode.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the RX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag ('unprepare RX') and go back to the IDLE state when it has stopped.

The receive buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to send more bytes to the slave than the slave is able to receive,these bytes will be discarded and the bytes will be NACKed by the slave. If this happens, an ERROR event will be generated.

The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is generated.

The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when the TWI slave has stopped. The TWI slave will clear the internal 'RX prepared' flag and go back to the IDLE state when it has stopped, see also Terminating an ongoing TWI transaction.

The TWI slave will generate an ACK after every byte received from the master. The RXD.AMOUNT register can be queried after a transaction to see how many bytes were received.

A typical TWI slave write command response is illustrated in The TWI slave responding to a write command. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave following a SUSPEND task.

Figure 5. The TWI slave responding to a write command
The TWI slave responding to a write command

Master repeated start sequence

An example of a repeated start sequence is one in which the TWI master writes two bytes to the slave followed by reading four bytes from the slave.

This is illustrated in A repeated start sequence, where the TWI master writes two bytes followed by reading four bytes from the slave .

It is here assumed that the receiver does not know in advance what the master wants to read, and that this information is provided in the first two bytes received in the write part of the repeated start sequence. To guarantee that the CPU is able to process the received data before the TWI slave starts to reply to the read command, the SUSPEND task is triggered via a shortcut from the READ event generated when the read command is received. When the CPU has processed the incoming data and prepared the correct data response, the CPU will resume the transaction by triggering the RESUME task.

Figure 6. A repeated start sequence, where the TWI master writes two bytes followed by reading four bytes from the slave
A repeated start sequence, where the TWI master writes two bytes followed by reading four bytes from the slave

Terminating an ongoing TWI transaction

In some situations, e.g. if the external TWI master is not responding correctly, it may be required to terminate an ongoing transaction.

This can be achieved by triggering the STOP task. In this situation a STOPPED event will be generated when the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state.

Low power

When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.

The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register.

Slave mode pin configuration

The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. PSEL.SCL and PSEL.SDA must only be configured when the TWI slave is disabled.

To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.

Table 2. GPIO configuration before enabling peripheral
TWI slave signal TWI slave pin Direction Output value Drive strength
SCL As specified in PSEL.SCL Input Not applicable S0D1
SDA As specified in PSEL.SDA Input Not applicable S0D1

Registers

Table 3. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x50008000
0x40008000

TWIS

TWIS0 : S
TWIS0 : NS

US

SA

Two-wire interface slave 0

   

0x50009000
0x40009000

TWIS

TWIS1 : S
TWIS1 : NS

US

SA

Two-wire interface slave 1

   

0x5000A000
0x4000A000

TWIS

TWIS2 : S
TWIS2 : NS

US

SA

Two-wire interface slave 2

   

0x5000B000
0x4000B000

TWIS

TWIS3 : S
TWIS3 : NS

US

SA

Two-wire interface slave 3

   
Table 4. Register overview
Register Offset Security Description
TASKS_STOP 0x014  

Stop TWI transaction

 
TASKS_SUSPEND 0x01C  

Suspend TWI transaction

 
TASKS_RESUME 0x020  

Resume TWI transaction

 
TASKS_PREPARERX 0x030  

Prepare the TWI slave to respond to a write command

 
TASKS_PREPARETX 0x034  

Prepare the TWI slave to respond to a read command

 
SUBSCRIBE_STOP 0x094  

Subscribe configuration for task STOP

 
SUBSCRIBE_SUSPEND 0x09C  

Subscribe configuration for task SUSPEND

 
SUBSCRIBE_RESUME 0x0A0  

Subscribe configuration for task RESUME

 
SUBSCRIBE_PREPARERX 0x0B0  

Subscribe configuration for task PREPARERX

 
SUBSCRIBE_PREPARETX 0x0B4  

Subscribe configuration for task PREPARETX

 
EVENTS_STOPPED 0x104  

TWI stopped

 
EVENTS_ERROR 0x124  

TWI error

 
EVENTS_RXSTARTED 0x14C  

Receive sequence started

 
EVENTS_TXSTARTED 0x150  

Transmit sequence started

 
EVENTS_WRITE 0x164  

Write command received

 
EVENTS_READ 0x168  

Read command received

 
PUBLISH_STOPPED 0x184  

Publish configuration for event STOPPED

 
PUBLISH_ERROR 0x1A4  

Publish configuration for event ERROR

 
PUBLISH_RXSTARTED 0x1CC  

Publish configuration for event RXSTARTED

 
PUBLISH_TXSTARTED 0x1D0  

Publish configuration for event TXSTARTED

 
PUBLISH_WRITE 0x1E4  

Publish configuration for event WRITE

 
PUBLISH_READ 0x1E8  

Publish configuration for event READ

 
SHORTS 0x200  

Shortcuts between local events and tasks

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
ERRORSRC 0x4D0  

Error source

 
MATCH 0x4D4  

Status register indicating which address had a match

 
ENABLE 0x500  

Enable TWIS

 
PSEL.SCL 0x508  

Pin select for SCL signal

 
PSEL.SDA 0x50C  

Pin select for SDA signal

 
RXD.PTR 0x534  

RXD Data pointer

 
RXD.MAXCNT 0x538  

Maximum number of bytes in RXD buffer

 
RXD.AMOUNT 0x53C  

Number of bytes transferred in the last RXD transaction

 
TXD.PTR 0x544  

TXD Data pointer

 
TXD.MAXCNT 0x548  

Maximum number of bytes in TXD buffer

 
TXD.AMOUNT 0x54C  

Number of bytes transferred in the last TXD transaction

 
ADDRESS[0] 0x588  

TWI slave address 0

 
ADDRESS[1] 0x58C  

TWI slave address 1

 
CONFIG 0x594  

Configuration register for the address match mechanism

 
ORC 0x5C0  

Over-read character. Character sent out in case of an over-read of the transmit buffer.

 

TASKS_STOP

Address offset: 0x014

Stop TWI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOP

   

Stop TWI transaction

     

Trigger

1

Trigger task

TASKS_SUSPEND

Address offset: 0x01C

Suspend TWI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_SUSPEND

   

Suspend TWI transaction

     

Trigger

1

Trigger task

TASKS_RESUME

Address offset: 0x020

Resume TWI transaction

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_RESUME

   

Resume TWI transaction

     

Trigger

1

Trigger task

TASKS_PREPARERX

Address offset: 0x030

Prepare the TWI slave to respond to a write command

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_PREPARERX

   

Prepare the TWI slave to respond to a write command

     

Trigger

1

Trigger task

TASKS_PREPARETX

Address offset: 0x034

Prepare the TWI slave to respond to a read command

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_PREPARETX

   

Prepare the TWI slave to respond to a read command

     

Trigger

1

Trigger task

SUBSCRIBE_STOP

Address offset: 0x094

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task STOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_SUSPEND

Address offset: 0x09C

Subscribe configuration for task SUSPEND

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task SUSPEND will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_RESUME

Address offset: 0x0A0

Subscribe configuration for task RESUME

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task RESUME will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_PREPARERX

Address offset: 0x0B0

Subscribe configuration for task PREPARERX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task PREPARERX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_PREPARETX

Address offset: 0x0B4

Subscribe configuration for task PREPARETX

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task PREPARETX will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_STOPPED

Address offset: 0x104

TWI stopped

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_STOPPED

   

TWI stopped

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_ERROR

Address offset: 0x124

TWI error

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_ERROR

   

TWI error

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_RXSTARTED

Address offset: 0x14C

Receive sequence started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RXSTARTED

   

Receive sequence started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_TXSTARTED

Address offset: 0x150

Transmit sequence started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TXSTARTED

   

Transmit sequence started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_WRITE

Address offset: 0x164

Write command received

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_WRITE

   

Write command received

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_READ

Address offset: 0x168

Read command received

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_READ

   

Read command received

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_STOPPED

Address offset: 0x184

Publish configuration for event STOPPED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event STOPPED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_ERROR

Address offset: 0x1A4

Publish configuration for event ERROR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event ERROR will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_RXSTARTED

Address offset: 0x1CC

Publish configuration for event RXSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event RXSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_TXSTARTED

Address offset: 0x1D0

Publish configuration for event TXSTARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event TXSTARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_WRITE

Address offset: 0x1E4

Publish configuration for event WRITE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event WRITE will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_READ

Address offset: 0x1E8

Publish configuration for event READ

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event READ will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                               B A                          
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

WRITE_SUSPEND

   

Shortcut between event WRITE and task SUSPEND

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

READ_SUSPEND

   

Shortcut between event READ and task SUSPEND

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID       H G         F E               B               A  
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

STOPPED

   

Enable or disable interrupt for event STOPPED

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

ERROR

   

Enable or disable interrupt for event ERROR

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

RXSTARTED

   

Enable or disable interrupt for event RXSTARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

TXSTARTED

   

Enable or disable interrupt for event TXSTARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

WRITE

   

Enable or disable interrupt for event WRITE

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

READ

   

Enable or disable interrupt for event READ

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID       H G         F E               B               A  
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

STOPPED

   

Write '1' to enable interrupt for event STOPPED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

ERROR

   

Write '1' to enable interrupt for event ERROR

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

RXSTARTED

   

Write '1' to enable interrupt for event RXSTARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

TXSTARTED

   

Write '1' to enable interrupt for event TXSTARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

WRITE

   

Write '1' to enable interrupt for event WRITE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

READ

   

Write '1' to enable interrupt for event READ

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID       H G         F E               B               A  
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

STOPPED

   

Write '1' to disable interrupt for event STOPPED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

ERROR

   

Write '1' to disable interrupt for event ERROR

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

RXSTARTED

   

Write '1' to disable interrupt for event RXSTARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

TXSTARTED

   

Write '1' to disable interrupt for event TXSTARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

WRITE

   

Write '1' to disable interrupt for event WRITE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

READ

   

Write '1' to disable interrupt for event READ

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

ERRORSRC

Address offset: 0x4D0

Error source

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         C B   A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

OVERFLOW

   

RX buffer overflow detected, and prevented

     

NotDetected

0

Error did not occur

     

Detected

1

Error occurred

B RW

DNACK

   

NACK sent after receiving a data byte

     

NotReceived

0

Error did not occur

     

Received

1

Error occurred

C RW

OVERREAD

   

TX buffer over-read detected, and prevented

     

NotDetected

0

Error did not occur

     

Detected

1

Error occurred

MATCH

Address offset: 0x4D4

Status register indicating which address had a match

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

MATCH

 

[0..1]

Which of the addresses in {ADDRESS} matched the incoming address

ENABLE

Address offset: 0x500

Enable TWIS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ENABLE

   

Enable or disable TWIS

     

Disabled

0

Disable TWIS

     

Enabled

9

Enable TWIS

PSEL.SCL

Address offset: 0x508

Pin select for SCL signal

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                   A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

C RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.SDA

Address offset: 0x50C

Pin select for SDA signal

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4