IPC — Inter-Processor Communication

The IPC peripheral is used to send and receive events between processors in the system.

Figure 1. IPC block diagram

Functional description

IPC block diagram illustrates the Inter-Processor Communication (IPC) peripheral. In a multi-core system, every CPU instance shall have one dedicated IPC peripheral. The IPC peripheral can be used to send and receive events to and from other IPC peripherals. An instance of the IPC peripheral can have #N send tasks and #N receive events. A single send task can be configured to signal an event on one or more channels, and a receive event can be configured to listen on one or more channels. The channels that are triggered in a send task can be configured through the SEND_CNF registers, and the channels that trigger a receive event is configured through the RECEIVE_CNF registers. A send task can be viewed as broadcasting events onto one or more channels, and a receive event can be seen as subscribing to a subset of channels. It is possible for multiple IPCs to trigger events onto the same channel at the same time, in this case it will look as a single event from the IPC subscriber.

The number of channels and send/receive events per IPC are implementation specific, and needs to be looked up in the reference manual for your specific device.

An event itself often does not contain any relevant information itself other than to signal that "something has occurred". Shared memory can be used to carry additional information between processors, e.g. in the form of command/event queues. It is up to software to assign a logical functionality to a channel. For instance one channel can be used to signal that a command is ready to be executed and any processor in the system can subscribe to that particular channel and decode/execute the command.

Figure 2. IPC SEND_CNF and RECEIVE_CNF

IPC SEND_CNF and RECEIVE_CNF illustrates how the SEND_CNF and RECEIVE_CNF registers work. A send task be connected to all channels, and a receive event can be connected to all channels.

Registers

Table 1. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x5002A000
0x4002A000

IPC

IPC : S
IPC : NS

US

NA

Interprocessor communication

   
Table 2. Register overview
Register Offset Security Description
TASKS_SEND[0] 0x000  

Trigger events on channel enabled in SEND_CNF[0].

 
TASKS_SEND[1] 0x004  

Trigger events on channel enabled in SEND_CNF[1].

 
TASKS_SEND[2] 0x008  

Trigger events on channel enabled in SEND_CNF[2].

 
TASKS_SEND[3] 0x00C  

Trigger events on channel enabled in SEND_CNF[3].

 
TASKS_SEND[4] 0x010  

Trigger events on channel enabled in SEND_CNF[4].

 
TASKS_SEND[5] 0x014  

Trigger events on channel enabled in SEND_CNF[5].

 
TASKS_SEND[6] 0x018  

Trigger events on channel enabled in SEND_CNF[6].

 
TASKS_SEND[7] 0x01C  

Trigger events on channel enabled in SEND_CNF[7].

 
SUBSCRIBE_SEND[0] 0x080  

Subscribe configuration for task SEND[0]

 
SUBSCRIBE_SEND[1] 0x084  

Subscribe configuration for task SEND[1]

 
SUBSCRIBE_SEND[2] 0x088  

Subscribe configuration for task SEND[2]

 
SUBSCRIBE_SEND[3] 0x08C  

Subscribe configuration for task SEND[3]

 
SUBSCRIBE_SEND[4] 0x090  

Subscribe configuration for task SEND[4]

 
SUBSCRIBE_SEND[5] 0x094  

Subscribe configuration for task SEND[5]

 
SUBSCRIBE_SEND[6] 0x098  

Subscribe configuration for task SEND[6]

 
SUBSCRIBE_SEND[7] 0x09C  

Subscribe configuration for task SEND[7]

 
EVENTS_RECEIVE[0] 0x100  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[1] 0x104  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[2] 0x108  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[3] 0x10C  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[4] 0x110  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[5] 0x114  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[6] 0x118  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
EVENTS_RECEIVE[7] 0x11C  

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

 
PUBLISH_RECEIVE[0] 0x180  

Publish configuration for event RECEIVE[0]

 
PUBLISH_RECEIVE[1] 0x184  

Publish configuration for event RECEIVE[1]

 
PUBLISH_RECEIVE[2] 0x188  

Publish configuration for event RECEIVE[2]

 
PUBLISH_RECEIVE[3] 0x18C  

Publish configuration for event RECEIVE[3]

 
PUBLISH_RECEIVE[4] 0x190  

Publish configuration for event RECEIVE[4]

 
PUBLISH_RECEIVE[5] 0x194  

Publish configuration for event RECEIVE[5]

 
PUBLISH_RECEIVE[6] 0x198  

Publish configuration for event RECEIVE[6]

 
PUBLISH_RECEIVE[7] 0x19C  

Publish configuration for event RECEIVE[7]

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
INTPEND 0x30C  

Pending interrupts

 
SEND_CNF[0] 0x510  

Send event configuration for TASKS_SEND[0].

 
SEND_CNF[1] 0x514  

Send event configuration for TASKS_SEND[1].

 
SEND_CNF[2] 0x518  

Send event configuration for TASKS_SEND[2].

 
SEND_CNF[3] 0x51C  

Send event configuration for TASKS_SEND[3].

 
SEND_CNF[4] 0x520  

Send event configuration for TASKS_SEND[4].

 
SEND_CNF[5] 0x524  

Send event configuration for TASKS_SEND[5].

 
SEND_CNF[6] 0x528  

Send event configuration for TASKS_SEND[6].

 
SEND_CNF[7] 0x52C  

Send event configuration for TASKS_SEND[7].

 
RECEIVE_CNF[0] 0x590  

Receive event configuration for EVENTS_RECEIVE[0].

 
RECEIVE_CNF[1] 0x594  

Receive event configuration for EVENTS_RECEIVE[1].

 
RECEIVE_CNF[2] 0x598  

Receive event configuration for EVENTS_RECEIVE[2].

 
RECEIVE_CNF[3] 0x59C  

Receive event configuration for EVENTS_RECEIVE[3].

 
RECEIVE_CNF[4] 0x5A0  

Receive event configuration for EVENTS_RECEIVE[4].

 
RECEIVE_CNF[5] 0x5A4  

Receive event configuration for EVENTS_RECEIVE[5].

 
RECEIVE_CNF[6] 0x5A8  

Receive event configuration for EVENTS_RECEIVE[6].

 
RECEIVE_CNF[7] 0x5AC  

Receive event configuration for EVENTS_RECEIVE[7].

 
GPMEM[0] 0x610  

General purpose memory.

 
GPMEM[1] 0x614  

General purpose memory.

 
GPMEM[2] 0x618  

General purpose memory.

 
GPMEM[3] 0x61C  

General purpose memory.

 

TASKS_SEND[n] (n=0..7)

Address offset: 0x000 + (n × 0x4)

Trigger events on channel enabled in SEND_CNF[n].

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_SEND

   

Trigger events on channel enabled in SEND_CNF[n].

     

Trigger

1

Trigger task

SUBSCRIBE_SEND[n] (n=0..7)

Address offset: 0x080 + (n × 0x4)

Subscribe configuration for task SEND[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task SEND[n] will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_RECEIVE[n] (n=0..7)

Address offset: 0x100 + (n × 0x4)

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RECEIVE

   

Event received on one or more of the enabled channels in RECEIVE_CNF[n].

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_RECEIVE[n] (n=0..7)

Address offset: 0x180 + (n × 0x4)

Publish configuration for event RECEIVE[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event RECEIVE[n] will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H RW

RECEIVE[i] (i=0..7)

   

Enable or disable interrupt for event RECEIVE[i]

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H RW

RECEIVE[i] (i=0..7)

   

Write '1' to enable interrupt for event RECEIVE[i]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H RW

RECEIVE[i] (i=0..7)

   

Write '1' to disable interrupt for event RECEIVE[i]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H R

RECEIVE[i] (i=0..7)

   

Read pending status of interrupt for event RECEIVE[i]

     

NotPending

0

Read: Not pending

     

Pending

1

Read: Pending

SEND_CNF[n] (n=0..7)

Address offset: 0x510 + (n × 0x4)

Send event configuration for TASKS_SEND[n].

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H RW

CHEN[i] (i=0..7)

   

Enable broadcasting on channel i.

     

Disable

0

Disable broadcast.

     

Enable

1

Enable broadcast.

RECEIVE_CNF[n] (n=0..7)

Address offset: 0x590 + (n × 0x4)

Receive event configuration for EVENTS_RECEIVE[n].

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-H RW

CHEN[i] (i=0..7)

   

Enable subscription to channel i.

     

Disable

0

Disable events.

     

Enable

1

Enable events.

GPMEM[n] (n=0..3)

Address offset: 0x610 + (n × 0x4)

General purpose memory.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

GPMEM

   

General purpose memory