SAADC — Successive approximation analog-to-digital converter

The SAADC is a differential successive approximation register (SAR) analog-to-digital converter.

Listed here are the main features of SAADC:

Overview

The ADC supports up to eight external analog input channels. It can be operated in a one-shot mode with sampling under software control, or a continuous conversion mode with a programmable sampling rate.

The analog inputs can be configured as eight single-ended inputs, four differential inputs or a combination of these. Each channel can be configured to select AIN0 to AIN7 pins, or the VDD_GPIO pin. Channels can be sampled individually in one-shot or continuous sampling modes, or, using scan mode, multiple channels can be sampled in sequence. Channels can also be oversampled to improve noise performance.

Figure 1. Simplified ADC block diagram
Simplified ADC block diagram

Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative input will be shorted to ground internally.

The assumption in single-ended mode is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern we recommend using differential measurement.

Digital output

The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as follows:

RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION - m)

where

V(P)
is the voltage at input P
V(N)
is the voltage at input N
GAIN
is the selected gain setting
REFERENCE
is the selected reference voltage

and m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff.

The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors due to high source impedance and sampling jitter. For battery measurement the DC errors are most noticeable.

The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input must be scaled accordingly.

The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we recommend running CALIBRATEOFFSET at regular intervals. The CALIBRATEDONE event will be fired when the calibration has been completed. Note that the DONE and RESULTDONE events will also be generated.

Analog inputs and channels

Up to eight analog input channels, CH[n](n=0..7), can be configured.

Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than one CH[n] is configured, the ADC enters scan mode.

An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also enables the particular channel.

An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register will have no effect unless differential mode is enabled, see MODE field in CH[n].CONFIG register.

If more than one of the CH[n].PSELP registers is set, the device enters scan mode. Input selections in scan mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if the particular scan channel is specified as differential, see MODE field in CH[n].CONFIG register.

Operation modes

The ADC input configuration supports one-shot mode, continuous mode and scan mode.

Note: Scan mode and oversampling cannot be combined.

The ADC indicates a single ongoing conversion via the register STATUS. During scan mode, oversampling, or continuous modes, more than a single conversion take place in the ADC. As consequence, the value reflected in STATUS register will toggle at the end of each single conversion.

One-shot mode

One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG registers.

Upon a SAMPLE task, the ADC starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the acquisition time.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For more information, see EasyDMA.

Continuous mode

Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task from one of the general purpose timers through the PPI system.

Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many channels are active:

fSAMPLE < 1/[tACQ + tconv]

The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the sample rate.

The SAMPLERATE timer mode cannot be combined with SCAN mode, and only one channel can be enabled in this mode.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA.

Oversampling

An accumulator in the ADC can be used to average noise on the analog input. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling, however, does not improve the integral non-linearity (INL), or differential non-linearity (DNL).

Oversampling and scan should not be combined, since oversampling and scan will average over input channels.

The accumulator is controlled in the OVERSAMPLE register. The SAMPLE task must be set 2OVERSAMPLE number of times before the result is written to RAM. This can be achieved by:

  • Configuring a fixed sampling rate using the local timer or a general purpose timer and the PPI system to trigger a SAMPLE task
  • Triggering SAMPLE 2OVERSAMPLE times from software
  • Enabling BURST mode

CH[n].CONFIG.BURST can be enabled to avoid setting SAMPLE task 2OVERSAMPLE times. With BURST = 1 the ADC will sample the input 2OVERSAMPLE times as fast as it can (actual timing: <(tACQ+tCONV)×2OVERSAMPLE). Thus, for the user it will just appear like the conversion took a bit longer time, but other than that, it is similar to one-shot mode.

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event signals that enough conversions have taken place for an oversampled result to get transferred into RAM. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA.

Scan mode

A channel is considered enabled if CH[n].PSELP is set. If more than one channel, CH[n], is enabled, the ADC enters scan mode.

In scan mode, one SAMPLE task will trigger one conversion per enabled channel. The time it takes to sample all channels is:

Total time < Sum(CH[x].tACQ+tCONV), x=0..enabled channels

A DONE event signals that one sample has been taken.

In this mode, the RESULTDONE event signals has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual values have been transferred into RAM by EasyDMA.

Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled provides an example of results placement in Data RAM, with an even RESULT.MAXCNT. In this example, channels 1, 2 and 5 are enabled, all others are disabled.

Figure 2. Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled
Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled

Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2 and 5 enabled provides an example of results placement in Data RAM, with an odd RESULT.MAXCNT. In this example, channels 1, 2 and 5 are enabled, all others are disabled. The last 32-bit word is populated only with one 16-bit result.

Figure 3. Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2 and 5 enabled
Example of RAM placement (odd RESULT.MAXCNT), channels 1, 2 and 5 enabled

EasyDMA

After configuring RESULT.PTR and RESULT.MAXCNT, the ADC resources are started by triggering the START task. The ADC is using EasyDMA to store results in a Result buffer in RAM.

The Result buffer is located at the address specified in the RESULT.PTR register. The RESULT.PTR register is double-buffered and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the Result buffer is specified in the RESULT.MAXCNT register and the ADC will generate an END event when it has filled up the Result buffer, see ADC. Results are stored in little-endian byte order in Data RAM. Every sample will be sign extended to 16 bit before stored in the Result buffer.

The ADC is stopped by triggering the STOP task. The STOP task will terminate an ongoing sampling. The ADC will generate a STOPPED event when it has stopped. If the ADC is already stopped when the STOP task is triggered, the STOPPED event will still be generated.

Figure 4. ADC
ADC

If the RESULT.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.

The EasyDMA will have finished accessing the RAM when the END or STOPPED event has been generated.

The RESULT.AMOUNT register can be read following an END event or a STOPPED event to see how many results have been transferred to the Result buffer in RAM since the START task was triggered.

In scan mode, SAMPLE tasks can be triggered once the START task is triggered. The END event is generated when the number of samples transferred to memory reaches the value specified by RESULT.MAXCNT. After an END event, the START task needs to be triggered again before new samples can be taken. Also make sure that the size of the Result buffer is large enough to have space for minimum one result from each of the enabled channels, by specifying RESULT.MAXCNT >= number of channels enabled. For more information about the scan mode, see Scan mode.

Resistor ladder

The ADC has an internal resistor string for positive and negative input.

See Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP). The resistors are controlled in the CH[n].CONFIG.RESP and CH[n].CONFIG.RESN registers.

Figure 5. Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP)
Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP

Reference

The ADC can use two different references, controlled in the REFSEL field of the CH[n].CONFIG register.

These are:

  • Internal reference
  • VDD_GPIO as reference

The internal reference results in an input range of ±0.6 V on the ADC core. VDD_GPIO as reference results in an input range of ±VDD_GPIO/4 on the ADC core. The gain block can be used to change the effective input range of the ADC.

Input range = (+- 0.6 V or +-VDD_GPIO/4)/Gain

For example, choosing VDD_GPIO as reference, single ended input (grounded negative input), and a gain of 1/4 the input range will be:

Input range = (VDD_GPIO/4)/(1/4) = VDD_GPIO

With internal reference, single ended input (grounded negative input), and a gain of 1/6 the input range will be:

Input range = (0.6 V)/(1/6) = 3.6 V

The AIN0-AIN7 inputs cannot exceed VDD_GPIO, or be lower than VSS.

Acquisition time

To sample the input voltage, the ADC connects a capacitor to the input.

For illustration, see Simplified ADC sample network. The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source (Rsource) resistance. For high source resistance the acquisition time should be increased, see Acquisition time.

Figure 6. Simplified ADC sample network
Simplified ADC sample network: Rsource, TACQ, ADC

Table 1. Acquisition time
TACQ [µs] Maximum source resistance [kOhm]
3 10
5 40
10 100
15 200
20 400
40 800

Limits event monitoring

A channel can be event monitored by configuring limit register CH[n].LIMIT.

If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will get fired.

Figure 7. Example of limits monitoring on channel 'n'
Example of limits monitoring on channel 'n'

Note that when setting the limits, CH[n].LIMIT.HIGH shall always be higher than or equal to CH[n].LIMIT.LOW . In other words, an event can be fired only when the input signal has been sampled outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range by swapping high and low limits.

The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a channel, the software shall simply ignore the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not.

Registers

Table 2. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x5000E000
0x4000E000

SAADC

SAADC : S
SAADC : NS

US

SA

Analog to digital converter

   
Table 3. Register overview
Register Offset Security Description
TASKS_START 0x000  

Start the ADC and prepare the result buffer in RAM

 
TASKS_SAMPLE 0x004  

Take one ADC sample, if scan is enabled all channels are sampled

 
TASKS_STOP 0x008  

Stop the ADC and terminate any on-going conversion

 
TASKS_CALIBRATEOFFSET 0x00C  

Starts offset auto-calibration

 
SUBSCRIBE_START 0x080  

Subscribe configuration for task START

 
SUBSCRIBE_SAMPLE 0x084  

Subscribe configuration for task SAMPLE

 
SUBSCRIBE_STOP 0x088  

Subscribe configuration for task STOP

 
SUBSCRIBE_CALIBRATEOFFSET 0x08C  

Subscribe configuration for task CALIBRATEOFFSET

 
EVENTS_STARTED 0x100  

The ADC has started

 
EVENTS_END 0x104  

The ADC has filled up the Result buffer

 
EVENTS_DONE 0x108  

A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.

 
EVENTS_RESULTDONE 0x10C  

A result is ready to get transferred to RAM.

 
EVENTS_CALIBRATEDONE 0x110  

Calibration is complete

 
EVENTS_STOPPED 0x114  

The ADC has stopped

 
EVENTS_CH[0].LIMITH 0x118  

Last results is equal or above CH[0].LIMIT.HIGH

 
EVENTS_CH[0].LIMITL 0x11C  

Last results is equal or below CH[0].LIMIT.LOW

 
EVENTS_CH[1].LIMITH 0x120  

Last results is equal or above CH[1].LIMIT.HIGH

 
EVENTS_CH[1].LIMITL 0x124  

Last results is equal or below CH[1].LIMIT.LOW

 
EVENTS_CH[2].LIMITH 0x128  

Last results is equal or above CH[2].LIMIT.HIGH

 
EVENTS_CH[2].LIMITL 0x12C  

Last results is equal or below CH[2].LIMIT.LOW

 
EVENTS_CH[3].LIMITH 0x130  

Last results is equal or above CH[3].LIMIT.HIGH

 
EVENTS_CH[3].LIMITL 0x134  

Last results is equal or below CH[3].LIMIT.LOW

 
EVENTS_CH[4].LIMITH 0x138  

Last results is equal or above CH[4].LIMIT.HIGH

 
EVENTS_CH[4].LIMITL 0x13C  

Last results is equal or below CH[4].LIMIT.LOW

 
EVENTS_CH[5].LIMITH 0x140  

Last results is equal or above CH[5].LIMIT.HIGH

 
EVENTS_CH[5].LIMITL 0x144  

Last results is equal or below CH[5].LIMIT.LOW

 
EVENTS_CH[6].LIMITH 0x148  

Last results is equal or above CH[6].LIMIT.HIGH

 
EVENTS_CH[6].LIMITL 0x14C  

Last results is equal or below CH[6].LIMIT.LOW

 
EVENTS_CH[7].LIMITH 0x150  

Last results is equal or above CH[7].LIMIT.HIGH

 
EVENTS_CH[7].LIMITL 0x154  

Last results is equal or below CH[7].LIMIT.LOW

 
PUBLISH_STARTED 0x180  

Publish configuration for event STARTED

 
PUBLISH_END 0x184  

Publish configuration for event END

 
PUBLISH_DONE 0x188  

Publish configuration for event DONE

 
PUBLISH_RESULTDONE 0x18C  

Publish configuration for event RESULTDONE

 
PUBLISH_CALIBRATEDONE 0x190  

Publish configuration for event CALIBRATEDONE

 
PUBLISH_STOPPED 0x194  

Publish configuration for event STOPPED

 
PUBLISH_CH[0].LIMITH 0x198  

Publish configuration for event CH[0].LIMITH

 
PUBLISH_CH[0].LIMITL 0x19C  

Publish configuration for event CH[0].LIMITL

 
PUBLISH_CH[1].LIMITH 0x1A0  

Publish configuration for event CH[1].LIMITH

 
PUBLISH_CH[1].LIMITL 0x1A4  

Publish configuration for event CH[1].LIMITL

 
PUBLISH_CH[2].LIMITH 0x1A8  

Publish configuration for event CH[2].LIMITH

 
PUBLISH_CH[2].LIMITL 0x1AC  

Publish configuration for event CH[2].LIMITL

 
PUBLISH_CH[3].LIMITH 0x1B0  

Publish configuration for event CH[3].LIMITH

 
PUBLISH_CH[3].LIMITL 0x1B4  

Publish configuration for event CH[3].LIMITL

 
PUBLISH_CH[4].LIMITH 0x1B8  

Publish configuration for event CH[4].LIMITH

 
PUBLISH_CH[4].LIMITL 0x1BC  

Publish configuration for event CH[4].LIMITL

 
PUBLISH_CH[5].LIMITH 0x1C0  

Publish configuration for event CH[5].LIMITH

 
PUBLISH_CH[5].LIMITL 0x1C4  

Publish configuration for event CH[5].LIMITL

 
PUBLISH_CH[6].LIMITH 0x1C8  

Publish configuration for event CH[6].LIMITH

 
PUBLISH_CH[6].LIMITL 0x1CC  

Publish configuration for event CH[6].LIMITL

 
PUBLISH_CH[7].LIMITH 0x1D0  

Publish configuration for event CH[7].LIMITH

 
PUBLISH_CH[7].LIMITL 0x1D4  

Publish configuration for event CH[7].LIMITL

 
INTEN 0x300  

Enable or disable interrupt

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
STATUS 0x400  

Status

 
ENABLE 0x500  

Enable or disable ADC

 
CH[0].PSELP 0x510  

Input positive pin selection for CH[0]

 
CH[0].PSELN 0x514  

Input negative pin selection for CH[0]

 
CH[0].CONFIG 0x518  

Input configuration for CH[0]

 
CH[0].LIMIT 0x51C  

High/low limits for event monitoring a channel

 
CH[1].PSELP 0x520  

Input positive pin selection for CH[1]

 
CH[1].PSELN 0x524  

Input negative pin selection for CH[1]

 
CH[1].CONFIG 0x528  

Input configuration for CH[1]

 
CH[1].LIMIT 0x52C  

High/low limits for event monitoring a channel

 
CH[2].PSELP 0x530  

Input positive pin selection for CH[2]

 
CH[2].PSELN 0x534  

Input negative pin selection for CH[2]

 
CH[2].CONFIG 0x538  

Input configuration for CH[2]

 
CH[2].LIMIT 0x53C  

High/low limits for event monitoring a channel

 
CH[3].PSELP 0x540  

Input positive pin selection for CH[3]

 
CH[3].PSELN 0x544  

Input negative pin selection for CH[3]

 
CH[3].CONFIG 0x548  

Input configuration for CH[3]

 
CH[3].LIMIT 0x54C  

High/low limits for event monitoring a channel

 
CH[4].PSELP 0x550  

Input positive pin selection for CH[4]

 
CH[4].PSELN 0x554  

Input negative pin selection for CH[4]

 
CH[4].CONFIG 0x558  

Input configuration for CH[4]

 
CH[4].LIMIT 0x55C  

High/low limits for event monitoring a channel

 
CH[5].PSELP 0x560  

Input positive pin selection for CH[5]

 
CH[5].PSELN 0x564  

Input negative pin selection for CH[5]

 
CH[5].CONFIG 0x568  

Input configuration for CH[5]

 
CH[5].LIMIT 0x56C  

High/low limits for event monitoring a channel

 
CH[6].PSELP 0x570  

Input positive pin selection for CH[6]

 
CH[6].PSELN 0x574  

Input negative pin selection for CH[6]

 
CH[6].CONFIG 0x578  

Input configuration for CH[6]

 
CH[6].LIMIT 0x57C  

High/low limits for event monitoring a channel

 
CH[7].PSELP 0x580  

Input positive pin selection for CH[7]

 
CH[7].PSELN 0x584  

Input negative pin selection for CH[7]

 
CH[7].CONFIG 0x588  

Input configuration for CH[7]

 
CH[7].LIMIT 0x58C  

High/low limits for event monitoring a channel

 
RESOLUTION 0x5F0  

Resolution configuration

 
OVERSAMPLE 0x5F4  

Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.

 
SAMPLERATE 0x5F8  

Controls normal or continuous sample rate

 
RESULT.PTR 0x62C  

Data pointer

 
RESULT.MAXCNT 0x630  

Maximum number of buffer words to transfer

 
RESULT.AMOUNT 0x634  

Number of buffer words transferred since last START

 

TASKS_START

Address offset: 0x000

Start the ADC and prepare the result buffer in RAM

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_START

   

Start the ADC and prepare the result buffer in RAM

     

Trigger

1

Trigger task

TASKS_SAMPLE

Address offset: 0x004

Take one ADC sample, if scan is enabled all channels are sampled

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_SAMPLE

   

Take one ADC sample, if scan is enabled all channels are sampled

     

Trigger

1

Trigger task

TASKS_STOP

Address offset: 0x008

Stop the ADC and terminate any on-going conversion

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOP

   

Stop the ADC and terminate any on-going conversion

     

Trigger

1

Trigger task

TASKS_CALIBRATEOFFSET

Address offset: 0x00C

Starts offset auto-calibration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_CALIBRATEOFFSET

   

Starts offset auto-calibration

     

Trigger

1

Trigger task

SUBSCRIBE_START

Address offset: 0x080

Subscribe configuration for task START

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task START will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_SAMPLE

Address offset: 0x084

Subscribe configuration for task SAMPLE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task SAMPLE will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOP

Address offset: 0x088

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task STOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_CALIBRATEOFFSET

Address offset: 0x08C

Subscribe configuration for task CALIBRATEOFFSET

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task CALIBRATEOFFSET will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_STARTED

Address offset: 0x100

The ADC has started

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_STARTED

   

The ADC has started

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_END

Address offset: 0x104

The ADC has filled up the Result buffer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_END

   

The ADC has filled up the Result buffer

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_DONE

Address offset: 0x108

A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_DONE

   

A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_RESULTDONE

Address offset: 0x10C

A result is ready to get transferred to RAM.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_RESULTDONE

   

A result is ready to get transferred to RAM.

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_CALIBRATEDONE

Address offset: 0x110

Calibration is complete

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_CALIBRATEDONE

   

Calibration is complete

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_STOPPED

Address offset: 0x114

The ADC has stopped

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_STOPPED

   

The ADC has stopped

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_CH[n].LIMITH (n=0..7)

Address offset: 0x118 + (n × 0x8)

Last results is equal or above CH[n].LIMIT.HIGH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

LIMITH

   

Last results is equal or above CH[n].LIMIT.HIGH

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_CH[n].LIMITL (n=0..7)

Address offset: 0x11C + (n × 0x8)

Last results is equal or below CH[n].LIMIT.LOW

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

LIMITL

   

Last results is equal or below CH[n].LIMIT.LOW

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_STARTED

Address offset: 0x180

Publish configuration for event STARTED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event STARTED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_END

Address offset: 0x184

Publish configuration for event END

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event END will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_DONE

Address offset: 0x188

Publish configuration for event DONE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event DONE will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_RESULTDONE

Address offset: 0x18C

Publish configuration for event RESULTDONE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event RESULTDONE will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_CALIBRATEDONE

Address offset: 0x190

Publish configuration for event CALIBRATEDONE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event CALIBRATEDONE will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_STOPPED

Address offset: 0x194

Publish configuration for event STOPPED

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event STOPPED will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_CH[n].LIMITH (n=0..7)

Address offset: 0x198 + (n × 0x8)

Publish configuration for event CH[n].LIMITH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event CH[n].LIMITH will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_CH[n].LIMITL (n=0..7)

Address offset: 0x19C + (n × 0x8)

Publish configuration for event CH[n].LIMITL

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event CH[n].LIMITL will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

STARTED

   

Enable or disable interrupt for event STARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

END

   

Enable or disable interrupt for event END

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

DONE

   

Enable or disable interrupt for event DONE

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

RESULTDONE

   

Enable or disable interrupt for event RESULTDONE

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

CALIBRATEDONE

   

Enable or disable interrupt for event CALIBRATEDONE

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

STOPPED

   

Enable or disable interrupt for event STOPPED

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

CH0LIMITH

   

Enable or disable interrupt for event CH0LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

CH0LIMITL

   

Enable or disable interrupt for event CH0LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

I RW

CH1LIMITH

   

Enable or disable interrupt for event CH1LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

J RW

CH1LIMITL

   

Enable or disable interrupt for event CH1LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

K RW

CH2LIMITH

   

Enable or disable interrupt for event CH2LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

L RW

CH2LIMITL

   

Enable or disable interrupt for event CH2LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

M RW

CH3LIMITH

   

Enable or disable interrupt for event CH3LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

N RW

CH3LIMITL

   

Enable or disable interrupt for event CH3LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

O RW

CH4LIMITH

   

Enable or disable interrupt for event CH4LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

P RW

CH4LIMITL

   

Enable or disable interrupt for event CH4LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

Q RW

CH5LIMITH

   

Enable or disable interrupt for event CH5LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

R RW

CH5LIMITL

   

Enable or disable interrupt for event CH5LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

S RW

CH6LIMITH

   

Enable or disable interrupt for event CH6LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

T RW

CH6LIMITL

   

Enable or disable interrupt for event CH6LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

U RW

CH7LIMITH

   

Enable or disable interrupt for event CH7LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

V RW

CH7LIMITL

   

Enable or disable interrupt for event CH7LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

STARTED

   

Write '1' to enable interrupt for event STARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

END

   

Write '1' to enable interrupt for event END

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

DONE

   

Write '1' to enable interrupt for event DONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

RESULTDONE

   

Write '1' to enable interrupt for event RESULTDONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

CALIBRATEDONE

   

Write '1' to enable interrupt for event CALIBRATEDONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

STOPPED

   

Write '1' to enable interrupt for event STOPPED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

CH0LIMITH

   

Write '1' to enable interrupt for event CH0LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

CH0LIMITL

   

Write '1' to enable interrupt for event CH0LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

CH1LIMITH

   

Write '1' to enable interrupt for event CH1LIMITH