RTC — Real-time counter

The real-time counter (RTC) module provides a generic, low power timer on the low frequency clock source (LFCLK).

Figure 1. RTC block diagram
RTC block diagram

The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, capture/compare registers, and a tick event generator for low power, tickless RTOS implementation.

Clock source

The RTC will run off the LFCLK.

When started, the RTC will automatically request the LFCLK source with RC oscillator if the LFCLK is not already running.

See CLOCK — Clock control for more information about clock sources.

Resolution versus overflow and the prescaler

The relationship between the prescaler, counter resolution and overflow is summarized in a table.

Table 1. RTC resolution versus overflow
Prescaler Counter resolution Overflow
0 30.517 μs 512 seconds
28-1 7812.5 μs 131072 seconds
212-1 125 ms 582.542 hours

Counter increment frequency is given by the following equation:


    fRTC [kHz] = 32.768 / (PRESCALER + 1 )
    

The PRESCALER register is read/write when the RTC is stopped. Once the RTC is started, the prescaler register is read-only and thus writing to it when the RTC is started has no effect.

The prescaler is restarted on tasks START, CLEAR and TRIGOVRFLW. That is, the prescaler value is latched to an internal register (<<PRESC>>) on these tasks.

Examples:

  1. Desired COUNTER frequency 100 Hz (10 ms counter period)

    PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327

    fRTC = 99.9 Hz

    10009.576 μs counter period

  2. Desired COUNTER frequency 8 Hz (125 ms counter period)

    PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095

    fRTC = 8 Hz

    125 ms counter period

Counter register

The counter increments on LFCLK when the internal PRESCALER register (<<PRESC>>) is 0x00. <<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. The TICK event is disabled by default.

Figure 2. Timing diagram - COUNTER_PRESCALER_0
Timing diagram - COUNTER_PRESCALER_0

Figure 3. Timing diagram - COUNTER_PRESCALER_1
Timing diagram - COUNTER_PRESCALER_1

Overflow

An OVRFLW event is generated on COUNTER register overflow (overflowing from 0xFFFFFF to 0).

The TRIGOVRFLW task will then set the COUNTER value to 0xFFFFF0, to allow software test of the overflow condition.

Note: The OVRFLW event is disabled by default.

Tick event

The TICK event enables low power tick-less RTOS implementation, as it optionally provides a regular interrupt source for an RTOS without the need to use the ARM® SysTick feature.

Using the TICK event, rather than the SysTick, allows the CPU to be powered down while still keeping RTOS scheduling active.

Note: The TICK event is disabled by default.

Event control

To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK from being requested when those events are triggered. This is managed using the EVTEN register.

For example, if the TICK event is not required for an application, it should be disabled, since its frequent occurrences may increase power consumption when HFCLK otherwise could be powered down for long periods of time.

This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface. The RTC task and event system is illustrated in the figure below.

Figure 4. Tasks, events and interrupts in the RTC
Tasks, events and interrupts in the RTC

Compare

The RTC implements one COMPARE event for every available capture/compare register.

When the COUNTER is incremented and then becomes equal to the value specified in the capture compare register CC[n], the corresponding compare event COMPARE[n] is generated.

When setting a compare register, the following behavior of the RTC COMPARE event should be noted:

  • If a CC register value is 0 when a CLEAR task is set, this will not trigger a COMPARE event.

    Figure 5. Timing diagram - COMPARE_CLEAR
    Timing diagram - COMPARE_CLEAR

  • If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event.

    Figure 6. Timing diagram - COMPARE_START
    Timing diagram - COMPARE_START

  • A COMPARE event occurs when a CC register is N and the COUNTER value transitions from N-1 to N.

    Figure 7. Timing diagram - COMPARE
    Timing diagram - COMPARE

  • If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2.

    Figure 8. Timing diagram - COMPARE_N+2
    Timing diagram - COMPARE_N+2

  • If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.

    Figure 9. Timing diagram - COMPARE_N+1
    Timing diagram - COMPARE_N+1

  • If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value greater than N+2 when the new value is written, there will be no event due to the old value.

    Figure 10. Timing diagram - COMPARE_N-1
    Timing diagram - COMPARE_N-1

Task and event jitter/delay

Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not synchronous to the faster PCLK16M.

Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain and is latched on read from an internal COUNTER register in the LFCLK domain. The COUNTER register is modified each time the RTC ticks. The registers are synchronised between the two clock domains (PCLK16M and LFCLK).

  1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15 μs and 46 μs for the remainder of the section.
    Figure 11. Timing diagram - DELAY_CLEAR
    Timing diagram - DELAY_CLEAR

    Figure 12. Timing diagram - DELAY_STOP
    Timing diagram - DELAY_STOP

  2. The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. In some cases, in particular if the RTC is started before the LFCLK is running, that timing can be up to ~250 μs. The software should therefore wait for the first TICK if it has to make sure the RTC is running. Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will start LFCLK, but the update will then be delayed by the same amount of time of up to ~250 µs. The figures show the smallest and largest delays on the START task, appearing as a +/-15 μs jitter on the first COUNTER increment.
    Figure 13. Timing diagram - JITTER_START-
    Timing diagram - JITTER_START-

    Figure 14. Timing diagram - JITTER_START+
    Timing diagram - JITTER_START+

Tables below summarize the jitter introduced on tasks and events.

Table 2. RTC jitter magnitudes on tasks
Task Delay
CLEAR, START, STOP, TRIGOVRFLOW +15 to 46 μs
Table 3. RTC jitter magnitudes on events
Operation/Function Jitter
START to COUNTER increment +/- 15 μs
COMPARE to COMPARE 1 +/- 62.5 ns

Reading the counter register

To read the COUNTER register, the internal <<COUNTER>> value is sampled.

To ensure that the <<COUNTER>> is safely sampled (considering that an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The read takes the CPU two cycles in addition, resulting in the COUNTER register read taking fixed five PCLK16M clock cycles.

Registers

Table 4. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x50014000
0x40014000

RTC

RTC0 : S
RTC0 : NS

US

NA

Real time counter 0

   

0x50015000
0x40015000

RTC

RTC1 : S
RTC1 : NS

US

NA

Real time counter 1

   
Table 5. Register overview
Register Offset Security Description
TASKS_START 0x000  

Start RTC counter

 
TASKS_STOP 0x004  

Stop RTC counter

 
TASKS_CLEAR 0x008  

Clear RTC counter

 
TASKS_TRIGOVRFLW 0x00C  

Set counter to 0xFFFFF0

 
SUBSCRIBE_START 0x080  

Subscribe configuration for task START

 
SUBSCRIBE_STOP 0x084  

Subscribe configuration for task STOP

 
SUBSCRIBE_CLEAR 0x088  

Subscribe configuration for task CLEAR

 
SUBSCRIBE_TRIGOVRFLW 0x08C  

Subscribe configuration for task TRIGOVRFLW

 
EVENTS_TICK 0x100  

Event on counter increment

 
EVENTS_OVRFLW 0x104  

Event on counter overflow

 
EVENTS_COMPARE[0] 0x140  

Compare event on CC[0] match

 
EVENTS_COMPARE[1] 0x144  

Compare event on CC[1] match

 
EVENTS_COMPARE[2] 0x148  

Compare event on CC[2] match

 
EVENTS_COMPARE[3] 0x14C  

Compare event on CC[3] match

 
PUBLISH_TICK 0x180  

Publish configuration for event TICK

 
PUBLISH_OVRFLW 0x184  

Publish configuration for event OVRFLW

 
PUBLISH_COMPARE[0] 0x1C0  

Publish configuration for event COMPARE[0]

 
PUBLISH_COMPARE[1] 0x1C4  

Publish configuration for event COMPARE[1]

 
PUBLISH_COMPARE[2] 0x1C8  

Publish configuration for event COMPARE[2]

 
PUBLISH_COMPARE[3] 0x1CC  

Publish configuration for event COMPARE[3]

 
SHORTS 0x200  

Shortcuts between local events and tasks

 
INTENSET 0x304  

Enable interrupt

 
INTENCLR 0x308  

Disable interrupt

 
EVTEN 0x340  

Enable or disable event routing

 
EVTENSET 0x344  

Enable event routing

 
EVTENCLR 0x348  

Disable event routing

 
COUNTER 0x504  

Current counter value

 
PRESCALER 0x508  

12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.

 
CC[n] 0x540  

Compare register n

 

TASKS_START

Address offset: 0x000

Start RTC counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_START

   

Start RTC counter

     

Trigger

1

Trigger task

TASKS_STOP

Address offset: 0x004

Stop RTC counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_STOP

   

Stop RTC counter

     

Trigger

1

Trigger task

TASKS_CLEAR

Address offset: 0x008

Clear RTC counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_CLEAR

   

Clear RTC counter

     

Trigger

1

Trigger task

TASKS_TRIGOVRFLW

Address offset: 0x00C

Set counter to 0xFFFFF0

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_TRIGOVRFLW

   

Set counter to 0xFFFFF0

     

Trigger

1

Trigger task

SUBSCRIBE_START

Address offset: 0x080

Subscribe configuration for task START

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task START will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_STOP

Address offset: 0x084

Subscribe configuration for task STOP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task STOP will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_CLEAR

Address offset: 0x088

Subscribe configuration for task CLEAR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task CLEAR will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

SUBSCRIBE_TRIGOVRFLW

Address offset: 0x08C

Subscribe configuration for task TRIGOVRFLW

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that task TRIGOVRFLW will subscribe to

B RW

EN

     

     

Disabled

0

Disable subscription

     

Enabled

1

Enable subscription

EVENTS_TICK

Address offset: 0x100

Event on counter increment

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_TICK

   

Event on counter increment

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_OVRFLW

Address offset: 0x104

Event on counter overflow

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_OVRFLW

   

Event on counter overflow

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

EVENTS_COMPARE[n] (n=0..3)

Address offset: 0x140 + (n × 0x4)

Compare event on CC[n] match

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_COMPARE

   

Compare event on CC[n] match

     

NotGenerated

0

Event not generated

     

Generated

1

Event generated

PUBLISH_TICK

Address offset: 0x180

Publish configuration for event TICK

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event TICK will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_OVRFLW

Address offset: 0x184

Publish configuration for event OVRFLW

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event OVRFLW will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

PUBLISH_COMPARE[n] (n=0..3)

Address offset: 0x1C0 + (n × 0x4)

Publish configuration for event COMPARE[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                       A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CHIDX

 

[15..0]

Channel that event COMPARE[n] will publish to.

B RW

EN

     

     

Disabled

0

Disable publishing

     

Enabled

1

Enable publishing

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                        
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         F E D C                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TICK

   

Write '1' to enable interrupt for event TICK

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

OVRFLW

   

Write '1' to enable interrupt for event OVRFLW

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C-F RW

COMPARE[i] (i=0..3)

   

Write '1' to enable interrupt for event COMPARE[i]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         F E D C                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TICK

   

Write '1' to disable interrupt for event TICK

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

OVRFLW

   

Write '1' to disable interrupt for event OVRFLW

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C-F RW

COMPARE[i] (i=0..3)

   

Write '1' to disable interrupt for event COMPARE[i]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

EVTEN

Address offset: 0x340

Enable or disable event routing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         F E D C                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TICK

   

Enable or disable event routing for event TICK

     

Disabled

0

Disable

     

Enabled

1

Disable

B RW

OVRFLW

   

Enable or disable event routing for event OVRFLW

     

Disabled

0

Disable

     

Enabled

1

Disable

C-F RW

COMPARE[i] (i=0..3)

   

Enable or disable event routing for event COMPARE[i]

     

Disabled

0

Disable

     

Enabled

1

Disable

EVTENSET

Address offset: 0x344

Enable event routing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         F E D C                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TICK

   

Write '1' to enable event routing for event TICK

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Set

1

Enable

B RW

OVRFLW

   

Write '1' to enable event routing for event OVRFLW

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Set

1

Enable

C-F RW

COMPARE[i] (i=0..3)

   

Write '1' to enable event routing for event COMPARE[i]

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Set

1

Enable

EVTENCLR

Address offset: 0x348

Disable event routing

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         F E D C                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TICK

   

Write '1' to disable event routing for event TICK

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Clear

1

Disable

B RW

OVRFLW

   

Write '1' to disable event routing for event OVRFLW

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Clear

1

Disable

C-F RW

COMPARE[i] (i=0..3)

   

Write '1' to disable event routing for event COMPARE[i]

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

     

Clear

1

Disable

COUNTER

Address offset: 0x504

Current counter value

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

COUNTER

   

Counter value

PRESCALER

Address offset: 0x508

12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                         A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

PRESCALER

   

Prescaler value

CC[n] (n=0..3)

Address offset: 0x540 + (n × 0x4)

Compare register n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

COMPARE

   

Compare value

Electrical specification

1 Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the numbers provided above.