AHB multilayer interconnect

On the AHB multilayer interconnect, the application CPU and all EasyDMA instances are AHB bus masters while RAM, cache and peripherals are AHB slaves. External MCU subsystems can be seen both as master and slave on the AHB multilayer interconnect.

Multiple AHB masters can access slave resources within the AHB multilayer interconnect as illustrated in Memory. Access rights to each of the AHB slaves are resolved using the natural priority of the different bus masters in the system.

Parent topic: Application core

AHB multilayer priorities

Each master connected to the AHB multilayer is assigned a default natural priority.

Table 1. AHB bus masters (listed from highest to lowest priority)
Bus master name Natural relative priority In/Out
System (CPU) Highest priority I/O
LTE Modem   I/O
I2S   I/O
PDM   I
SPIM0/SPIS0/TWIM0/TWIS0/UARTE0   I/O
SPIM1/SPIS1/TWIM1/TWIS1/UARTE1   I/O
SPIM2/SPIS2/TWIM2/TWIS2/UARTE2   I/O
SPIM3/SPIS3/TWIM3/TWIS3/UARTE3   I/O
SAADC   I
PWM0   O
PWM1   O
PWM2   O
PWM3   O
CC310 Lowest priority I/O