VMC — Volatile memory controller

The volatile memory controller (VMC) provides power control of RAM blocks.

Each of the available RAM blocks, which can contain multiple RAM sections, can be turned on or off independently in System ON mode, using the RAM[n]registers. These registers also control if a RAM block, or some of its sections, is retained in System OFF mode. See Memory chapter for more information about RAM blocks and sections.

Registers

Table 1. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration

0x5003A000
0x4003A000

VMC

VMC : S
VMC : NS

US

NA

Volatile memory controller

   
Table 2. Register overview
Register Offset Security Description
RAM[0].POWER 0x600  

RAM0 power control register

 
RAM[0].POWERSET 0x604  

RAM0 power control set register

 
RAM[0].POWERCLR 0x608  

RAM0 power control clear register

 
RAM[1].POWER 0x610  

RAM1 power control register

 
RAM[1].POWERSET 0x614  

RAM1 power control set register

 
RAM[1].POWERCLR 0x618  

RAM1 power control clear register

 
RAM[2].POWER 0x620  

RAM2 power control register

 
RAM[2].POWERSET 0x624  

RAM2 power control set register

 
RAM[2].POWERCLR 0x628  

RAM2 power control clear register

 
RAM[3].POWER 0x630  

RAM3 power control register

 
RAM[3].POWERSET 0x634  

RAM3 power control set register

 
RAM[3].POWERCLR 0x638  

RAM3 power control clear register

 
RAM[4].POWER 0x640  

RAM4 power control register

 
RAM[4].POWERSET 0x644  

RAM4 power control set register

 
RAM[4].POWERCLR 0x648  

RAM4 power control clear register

 
RAM[5].POWER 0x650  

RAM5 power control register

 
RAM[5].POWERSET 0x654  

RAM5 power control set register

 
RAM[5].POWERCLR 0x658  

RAM5 power control clear register

 
RAM[6].POWER 0x660  

RAM6 power control register

 
RAM[6].POWERSET 0x664  

RAM6 power control set register

 
RAM[6].POWERCLR 0x668  

RAM6 power control clear register

 
RAM[7].POWER 0x670  

RAM7 power control register

 
RAM[7].POWERSET 0x674  

RAM7 power control set register

 
RAM[7].POWERCLR 0x678  

RAM7 power control clear register

 

RAM[n].POWER (n=0..7)

Address offset: 0x600 + (n × 0x10)

RAMn power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         H G F E                         D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-D RW

S[i]POWER (i=0..3)

   

Keep RAM section Si of RAM n on or off in System ON mode

All RAM sections will be switched off in System OFF mode

     

Off

0

Off

     

On

1

On

E-H RW

S[i]RETENTION (i=0..3)

   

Keep retention on RAM section Si of RAM n when RAM section is switched off

     

Off

0

Off

     

On

1

On

RAM[n].POWERSET (n=0..7)

Address offset: 0x604 + (n × 0x10)

RAMn power control set register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         H G F E                         D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-D W

S[i]POWER (i=0..3)

   

Keep RAM section Si of RAM n on or off in System ON mode

     

On

1

On

E-H W

S[i]RETENTION (i=0..3)

   

Keep retention on RAM section Si of RAM n when RAM section is switched off

     

On

1

On

RAM[n].POWERCLR (n=0..7)

Address offset: 0x608 + (n × 0x10)

RAMn power control clear register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                         H G F E                         D C B A
Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A-D W

S[i]POWER (i=0..3)

   

Keep RAM section Si of RAM n on or off in System ON mode

     

Off

1

Off

E-H W

S[i]RETENTION (i=0..3)

   

Keep retention on RAM section Si of RAM n when RAM section is switched off

     

Off

1

Off