VMC — Volatile memory controller

The volatile memory controller (VMC) provides power control of RAM blocks.

Each of the available RAM blocks, which can contain multiple RAM sections, can be turned on or off independently in System ON mode, using the RAM[n]registers. These registers also control if a RAM block, or some of its sections, is retained in System OFF mode. See Memory chapter for more information about RAM blocks and sections.

Note: Powering up a RAM block takes typically 10 cycles. Thus, it is recommended reading the POWER register before accessing a RAM block that has been recently powered on.

Registers

Table 1. Instances
Base address	Peripheral	Instance	Secure mapping	DMA security	Description	Configuration
0x5003A000 0x4003A000	VMC	VMC : S VMC : NS	US	NA	Volatile memory controller

Table 2. Register overview
Register	Offset	Description
RAM[n].POWER	0x600	RAMn power control register
RAM[n].POWERSET	0x604	RAMn power control set register
RAM[n].POWERCLR	0x608	RAMn power control clear register

RAM[n].POWER (n=0..7)

Address offset: 0x600 + (n × 0x10)

RAMn power control register

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																H	G	F	E													D	C	B	A
Reset 0x0000FFFF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A-D	RW	S[i]POWER (i=0..3)										Keep RAM section Si of RAM n on or off in System ON mode All RAM sections will be switched off in System OFF mode
			Off	0								Off
			On	1								On
E-H	RW	S[i]RETENTION (i=0..3)										Keep retention on RAM section Si of RAM n when RAM section is switched off
			Off	0								Off
			On	1								On

RAM[n].POWERSET (n=0..7)

Address offset: 0x604 + (n × 0x10)

RAMn power control set register

When read, this register will return the value of the POWER register.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																H	G	F	E													D	C	B	A
Reset 0x0000FFFF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A-D	W	S[i]POWER (i=0..3)										Keep RAM section Si of RAM n on or off in System ON mode
			On	1								On
E-H	W	S[i]RETENTION (i=0..3)										Keep retention on RAM section Si of RAM n when RAM section is switched off
			On	1								On

RAM[n].POWERCLR (n=0..7)

Address offset: 0x608 + (n × 0x10)

RAMn power control clear register

When read, this register will return the value of the POWER register.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																H	G	F	E													D	C	B	A
Reset 0x0000FFFF				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A-D	W	S[i]POWER (i=0..3)										Keep RAM section Si of RAM n on or off in System ON mode
			Off	1								Off
E-H	W	S[i]RETENTION (i=0..3)										Keep retention on RAM section Si of RAM n when RAM section is switched off
			Off	1								Off