New and inherited anomalies

Table 1. New and inherited anomalies
ID	Module	Description	Inherited from Revision 1
1	I2S	Excessive power consumption after using STOP task	X
2	NVMC	CPU code execution from RAM halted during flash page erase operation	X
4	GPIO	Bits in GPIO LATCH register are incorrectly set to 1	X
6	POWER	SLEEPENTER and SLEEPEXIT events asserted after pin reset	X
7	KMU	Subsequent accesses between info_mem and main_mem of the flash may not work properly	X
9	SAADC	Reduced SFDR	X
15	REGULATORS	Supply regulators default to LDO mode after reset	X
21	NVMC	Disabling instruction cache causes skip of next instruction	X
23	UART	TASKS_RESUME impacts UARTE	X
24	NVMC	CPU is not halted for page erase in debug session	X
26	CLOCK, LFXO	System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED	X
28	SAADC	Events are not generated when switching from scan mode to no-scan mode	X
29	Debug and Trace	System reset does not work	X
30	PWM	False SEQEND[0] and SEQEND[1] events are generated	X
31	LFXO	LFXO startup fails	X
32	Debug and Trace	Debug power-up request is not acknowledged	X
33	DPPI	Non-secure code can detect secure events	X

[1] I2S: Excessive power consumption after using STOP task
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[2] NVMC: CPU code execution from RAM halted during flash page erase operation
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[9] SAADC: Reduced SFDR
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[15] REGULATORS: Supply regulators default to LDO mode after reset
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[21] NVMC: Disabling instruction cache causes skip of next instruction
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[23] UART: TASKS_RESUME impacts UARTE
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[24] NVMC: CPU is not halted for page erase in debug session
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[28] SAADC: Events are not generated when switching from scan mode to no-scan mode
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[29] Debug and Trace: System reset does not work
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[30] PWM: False SEQEND[0] and SEQEND[1] events are generated
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[31] LFXO: LFXO startup fails
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[32] Debug and Trace: Debug power-up request is not acknowledged
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

[33] DPPI: Non-secure code can detect secure events
This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.