This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.
It was inherited from the previous IC revision
Revision 1.
Symptoms
In the CTRL/STAT register of the debug port (see
ARM CoreSight SoC-400 Technical Reference Manual, revision r3p2):
- CDBGPWRUPREQ powers up the system but does not assert CDBGPWRUPACK.
- CSYSPWRUPREQ does not trigger any power requests but asserts CDBGPWRUPACK and CSYSPWRUPACK.
Conditions
Always when starting a debug session.
Consequences
If the debug probe writes the debug port CTRL/STAT.DBGPWRUPREQ and waits on CTRL/STAT.DBGPWRUPACK, it does not finish.
Workaround
When enabling debug domain power, write CTRL/STAT.DBGPWRUPREQ and CTRL/STAT.SYSPWRUPREQ.