This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.
The CPU skips first instruction after instruction cache is disabled.
The code executes instructions to disable the instruction cache.
The program does not execute as expected.
_attribute_((aligned(ICACHE_LINE_SIZE)))
void icache_disable(void) {
int key = DisableInterrupts();
__ISB();
NRF_NVMC->ICACHECNF = 0;
__ISB();
EnableInterrupts(key);
}