[4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1

This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

It was inherited from the previous IC revision Revision 1.


The GPIO.LATCH[n] register is unexpectedly set to 1 (Latched).


Set GPIO.PIN_CNF[n].SENSE at low level (3) at the same time as PIN_CNF[n].INPUT is set to Connect (0).


The GPIO.LATCH[n] register is set to 1 (Latched). This could have side effects, depending on how the chip is configured to use this LATCH register.


Always configure PIN_CNF[n].INPUT before PIN_CNF[n].SENSE.