Errata nRF9160 - Debug and Trace: System reset does not work

This anomaly applies to IC Rev. Revision 2, build codes SICA-B1A, SIBA-B1A, SIAA-B1A.

It was inherited from the previous IC revision Revision 1.

Symptoms

Debugger is unable to trigger a system reset through AIRCR.SYSRESETREQ.

The CPU is running non-secure code and has set the AIRCR.SYSRESETREQ bit

Reset request is ignored.

Complete the following steps:

Halt the CPU through a connected debugger.
Force the processor into secure mode by setting DSCSR.SDS (see Register Specification in Arm®v8-M Architecture Reference Manual):
```
      SCB_DSCSR = (SCB_DSCSR &  ~(1 << 17)) | 1 << 16; 
     
```
This sets bit 17 (CDSKEY) to 0 to allow writes to CDS and bit 16 (CDS) to 1 to force secure execution.
Reset CPU through AIRCR.SYSRESETREQ (see Register Specification in Arm®v8-M Architecture Reference Manual).
The system resets.