v1.0

Pin description

Each nRF9160 pin has specified functions and design recommendations. The detailed design recommendations are provided in Hardware integration.

The following table describes the functions of the nRF9160 pins.

Table 1. Pin assignments
Pin no Pin name Function Description
1 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
2 P0.05 GPIO Digital I/O, VDD_GPIO level.
3 P0.06
4 P0.07
5–9 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
10 Reserved Connect thermally and mechanically to the application board, but leave electrically unconnected.
11 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
12 VDD_GPIO GPIO power supply input and logic level for GPIOs.
13 DEC0 nRF9160-internal supply capacitor connection.
14 GND_Shield Microshield ground. Connect to VSS (pin 103) and application board ground.
15 P0.08 GPIO Digital I/O, VDD_GPIO level.
16 P0.09
17 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
18 P0.10 GPIO Digital I/O, VDD_GPIO level.
19 P0.11
20 P0.12
21 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
22 VDD2 nRF9160's Power Amplifier (PA) PMU supply input. Must be at the same voltage level as VDD1 (pin 102) supply for the System on Chip (SoC).
23 P0.13 GPIO Digital I/O and analog input, VDD_GPIO level.
24 P0.14
25 P0.15
26 P0.16
27 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
28 P0.17 GPIO Digital I/O and analog input, VDD_GPIO level.
29 P0.18
30 P0.19
31 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
32 nRESET System reset SoC reset.
33 SWDCLK Serial Wire Debug (SWD) SWD and programming clock input.
34 SWDIO SWD and programming interface.
35 P0.20 GPIO Digital I/O and analog input, VDD_GPIO level.
36 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
37 P0.21 GPIO Digital I/O and trace buffer clock, VDD_GPIO level.
38 P0.22 Digital I/O, VDD_GPIO level.
39 P0.23
40 P0.24
41 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
42 P0.25 GPIO Digital I/O, VDD_GPIO level.
43 SIM_RST Subscriber Identity Module (SIM) SIM reset.
44 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
45 SIM_DET SIM SIM detect (currently not a supported feature).
46 SIM_CLK SIM clock.
47 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
48 SIM_IO SIM SIM data.
49 SIM_1V8 SIM card's 1.8 V power supply output.
50 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
51 Reserved Reserved Connect thermally and mechanically to the application board, but leave electrically unconnected.
52 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
53 MAGPIO2 GPIO Digital I/O. Controllable by application processor and LTE modem, fixed 1.8 V.
54 MAGPIO1
55 MAGPIO0
56 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
57 VIO RFFE ctrl Digital I/O. MIPI RF Front-End Control Interface (RFFE) VIO compatible, fixed 1.8 V.
58 SCLK Digital I/O. MIPI RFFE CLK compatible, fixed 1.8 V.
59 SDATA Digital I/O. MIPI RFFE DATA compatible, fixed 1.8 V.
60 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
61 ANT RF Cellular antenna port, 50 Ω.
62 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
63 GND_Shield
64 AUX RF Loopback port for cellular antenna. A matching network external to the module is recommended.
65 GND_Shield Power Microshield ground, connect to VSS (pin 103) and application board ground.
66 GND_Shield
67 GPS RF Global Positioning System (GPS) receiver antenna port, 50 Ω.
68 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
69 GND_Shield
70 Reserved Reserved Connect thermally and mechanically to the application board, but leave electrically unconnected.
71 Reserved
72 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
73 Reserved Reserved Connect thermally or mechanically to the application board, but leave electrically unconnected.
74–82 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
83 P0.26 GPIO Digital I/O, VDD_GPIO level.
84 P0.27
85 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
86 P0.28 GPIO Digital I/O, VDD_GPIO level.
87 P0.29
88 P0.30
89 P0.31
90 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
91 COEX2 GPIO Controlled by modem.
92 COEX1
93 COEX0
94 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
95 P0.00 GPIO Digital I/O, VDD_GPIO level.
96 P0.01
97 P0.02
98 GND_Shield Power Microshield ground. Connect to VSS (pin 103) and application board ground.
99 P0.03 GPIO Digital I/O, VDD_GPIO level.
100 P0.04 Digital I/O, VDD_GPIO level.
101 ENABLE Control < 0.4 V disable, > 0.8 x VDD1 enable.
102 VDD1 Power nRF9160 SoC PMU supply input. Must be at the same voltage level as VDD2's (pin 22) supply for PA.
103 VSS nRF9160 ground plane. Ensure the connection to the application board ground is solid for good electrical, thermal, and mechanical robustness performance.
104–127 Reserved Reserved Connect thermally and mechanically to the application board, but leave electrically unconnected.