VDD_GPIO (pin 12) is the supply for application GPIOs P0.00–P0.31 and the COEX interface (pins 91–93) that is provided externally.

The operating voltage of VDD_GPIO ranges from 1.8 to 3.6 V and is independent of the VDD supply. The GPIOs have software-configurable drive modes. In standard drive mode, pin sink and source currents are approximately 0.5 mA. In high drive mode, pin currents are 3 to 5 mA. The standard drive mode is operational over the voltage range of 1.8 to 3.6 V. High drive mode is operational over the voltage range of 1.8 to 3.6 V, but 5 mA drive current requires VDD_GPIO voltage of ≥ 2.7 V.

Standard drive is recommended because lower current results in better EMI performance and interoperability with other application board peripherals. With standard drive, the end product's performance regarding items, such as LTE radiated spurious emissions and LTE receiver radiated sensitivity, is typically somewhat better than with high drive.

Unlike the current consumption of VDD, VDD_GPIO's current consumption is mostly controlled by the end product design. This is because VDD_GPIO supplies the application GPIOs which are controlled by the application software provided by the integrator. If the GPIOs are not significantly stressed in the device, VDD_GPIO can have a simple power supply strategy. However, if the end product has high momentary current draw from the GPIOs, VDD_GPIO's capability must be designed to comply with it. In the worst case, the momentary concurrent current consumption of all GPIOs should not peak higher than approximately 100 mA. Regardless of the VDD_GPIO's supply capability, it is not recommended to have long periods of high concurrent consumption because it increases the risk of reducing the device's lifetime.

Recommended VDD_GPIO decoupling capacitors are shown in nRF9160 application component recommendations.

The following restrictions apply to the VDD_GPIO pin: