New and inherited anomalies

The following anomalies are present in revision Engineering A of the nRF5340 chip.

Table 1. New and inherited anomalies
ID Domain Module Description New in Engineering A
3 Application SAADC VDDHDIV5 is not functional X
4 Application CLOCK Changing application core frequency register HFCLKCTRL requires additional register initialization X
5 Application TAD Trace is not functional when application core is running at 128 MHz X
6 Network NVMC Disabling instruction cache causes skip of next instruction X
7 Application USBD USBD is not functional X
8 Application WDT WDT1 is not functional X
9 Application TAD TPIU is missing from ROM table X
10 Network CCM Reading CNFPTR, INPTR, OUTPTR, and SCRATCHPTR pointers returns incorrect address X
11 Network ACL Reading ACL[n].ADDR returns incorrect address X
12 Application QSPI SCKFREQ is not functional at 96 MHz X
13 Application, Network GPIO Bits in LATCH register are incorrectly set to 1 X
14 Network TIMER CC[6] and CC[7] are not functional X
15 Application, Network UARTE Odd parity setting is not functional X
16 Network RADIO POWER register is not functional X
18 Application I2S 32-bit sample widths and 8-bit sample in a 16-bit half-frame are not functional X
19 Application SPU Flash memory space is divided into 32 regions of 32 KiB X
20 Application, Network RTC TASKS_CAPTURE[n], SUBSCRIBE_CAPTURE[n], and SHORTS registers are not functional X
21 Application, Network TWIM 1000 kbps baud rate is not functional X
22 Application SPU CPULOCK register is not functional X
23 Application SAADC Events are not generated when switching from scan mode to no-scan mode with BURST enabled X
26 Application, Network CTRL-AP APPROTECT.DISABLE and SECUREAPPROTECT.DISABLE registers are not functional X
27 Application, Network CTRL-AP STATUS register is not functional X
28 Application, Network TIMER INTEN register is not functional X
29 Network SWI SWIRQ is not functional X
30 Network RESET LCTRLAP field in RESETREAS register is not functional X
32 Network GPIO GPIO pins assigned to network core do not retain their state in System OFF mode X
33 Application CLOCK LFRC frequency starts drifting even if calibration task is triggered X
37 Application, Network TWIM First clock pulse after clock stretching may be too long or too short X
42 Application CLOCK Reset value of HFCLKCTRL is invalid X
43 Application QSPI Reading QSPI registers after XIP might halt application CPU X
44 Application, Network UARTE TASKS_RESUME impacts UARTE X
45 Application SPIM Receive is not functional at 32 Mbps X
46 Application CLOCK LFRC has higher current consumption X
47 Application, Network TWIM I2C timing spec is violated at 400 kHz X
49 Application, Network POWER SLEEPENTER and SLEEPEXIT events are asserted after pin reset X
50 Application SPU Arm TrustZone region numbers for FICR, UICR, CACHEINFO, and CACHEDATA are incorrect X
51 Application SPU Accessing FICR, UICR, CACHEINFO, or CACHEDATA from non-secure state gives bus error X
53 Application REGULATORS Current consumption in normal voltage mode is higher in System ON idle X
54 Network REGULATORS Current consumption in normal voltage mode is higher in System ON idle and System OFF X
55 Application, Network RESET Bits in RESETREAS are set when they should not be X
57 Application I2S EVENTS_FRAMESTART and PUBLISH_FRAMESTART registers are not functional X
58 Application I2S BYPASS in CONFIG.CLKCONFIG is not functional X
59 Application QDEC QDEC0 is not functional X
62 Application, Network UICR HFXOCNT register is not functional X
64 Application REGULATORS VREGMAIN has invalid configuration when CPU is running X
65 Application SAADC Events are not generated when switching from scan mode to no-scan mode with BURST disabled X
69 Application REGULATORS VREGMAIN configuration is not retained in System OFF X
72 Application REGULATORS Current consumption in high voltage mode is higher in System ON idle and System OFF X
73 Application, Network TIMER ONESHOTEN[n] registers are located at an incorrect address offset X
74 Application, Network TIMER COMPARE[i]_STOP is located at an incorrect bit number in the SHORTS register X
79 Application QDEC QDEC1 is not functional X
80 Application PWM PWM3 is not functional X
81 Application SPIM SPIM2 and SPIM3 are not functional X
82 Application TWIM TWIM2 and TWIM3 are not functional X
83 Application SPIS SPIS2 and SPIS3 are not functional X
84 Application UARTE UARTE2 and UARTE3 are not functional X