[13] GPIO: Bits in LATCH register are incorrectly set to 1

This anomaly applies to IC Rev. Engineering A, build codes QKAA-AB0.

Domains

Application, Network

Symptoms

The GPIO.LATCH[n] register is unexpectedly set to 1 (Latched).

Conditions

GPIO.PIN_CNF[n].SENSE is set to low level (3) at the same time as PIN_CNF[n].INPUT is set to Connect (0).

Consequences

The GPIO.LATCH[n] register is set to 1 (Latched). This could have side effects, depending on how the chip is configured to use this LATCH register.

Workaround

Always configure PIN_CNF[n].INPUT before PIN_CNF[n].SENSE.