[9] TAD: TPIU is missing from ROM table

Initialize trace modules manually with the following code and, if necessary, use debug probe-dependent mechanisms to set up extra ROM table addresses.

#define ARM_CS_LOCK 0x00000000
#define ARM_CS_UNLOCK 0xC5ACCE55
 
#define ETM_TRCPRGCTLR_Enable (1 << 0)
#define ETM_TRCCONFIGR_BranchBroadcast_En (1 << 3)
#define ETM_TRCCONFIGR_Timestamp_En (1 << 11)
#define ETM_TRCCONFIGR_ReturnStack_En (1 << 12)
#define ETM_TRCEVENTCTL0R_Sel0_Resources2 (2 << 0)
#define ETM_TRCEVENTCTL1R_Insten_Event0_En (1 << 0)
#define ETM_TRCRSCTLR2_Select_Resource0 (1 << 0)
#define ETM_TRCRSCTLR2_Group_Resource0 (1 << 16)
#define ETM_TRCSTALLCTLR_Level_ZeroInvasion (0 << 0)
#define ETM_TRCSYNCPR_Period_12 (12 << 0)
#define ETM_TRCTSCTLR_Event_0 (0 << 0)
#define ETM_TRCTRACEIDR_TraceId (1 << 0)
#define ETM_TRCVICTLR_StartStopLogic_On (1 << 9)
#define ETM_TRCVICTLR_Event_0 (1 << 0)
 
#define ETM_TRCPRGCTLR 0xE0041004
#define ETM_TRCCONFIGR 0xE0041010
#define ETM_TRCEVENTCTL0R 0xE0041020
#define ETM_TRCEVENTCTL1R 0xE0041024
#define ETM_TRCSTALLCTLR 0xE004102C
#define ETM_TRCTSCTLR 0xE0041030
#define ETM_TRCSYNCPR 0xE0041034
#define ETM_TRCTRACEIDR 0xE0041040
#define ETM_TRCVICTLR 0xE0041080
#define ETM_TRCRSCTLR2 0xE0041208
#define ETM_TRCLAR 0xE0041FB0
 
#define TPIU_SPPR_ParallelMode 0x0
#define TPIU_FFCR_EnFCont (1 << 1)
 
#define TPIU_CSPSR 0xE0040004
#define TPIU_SPPR 0xE00400F0
#define TPIU_FFCR 0xE0040304
#define TPIU_LAR 0xE0040FB0
 
void etm_init(void)
{
    uint32_t etm_stable = 0x00000000;
        
    // Basic programming of ETM
    *(uint32_t*)(ETM_TRCLAR) = ARM_CS_UNLOCK;
    *(uint32_t*)(ETM_TRCCONFIGR) = ETM_TRCCONFIGR_Timestamp_En | ETM_TRCCONFIGR_ReturnStack_En;
    *(uint32_t*)(ETM_TRCEVENTCTL0R) = ETM_TRCEVENTCTL0R_Sel0_Resources2;
    *(uint32_t*)(ETM_TRCEVENTCTL1R) = ETM_TRCEVENTCTL1R_Insten_Event0_En;
    *(uint32_t*)(ETM_TRCRSCTLR2) = ETM_TRCRSCTLR2_Select_Resource0 | ETM_TRCRSCTLR2_Group_Resource0;
    *(uint32_t*)(ETM_TRCSTALLCTLR) = ETM_TRCSTALLCTLR_Level_ZeroInvasion;
    *(uint32_t*)(ETM_TRCSYNCPR) = ETM_TRCSYNCPR_Period_12;
    *(uint32_t*)(ETM_TRCTRACEIDR) = ETM_TRCTRACEIDR_TraceId;
    *(uint32_t*)(ETM_TRCTSCTLR) = ETM_TRCTSCTLR_Event_0;
    *(uint32_t*)(ETM_TRCVICTLR) = ETM_TRCVICTLR_StartStopLogic_On | ETM_TRCVICTLR_Event_0;
    
    // Enable ETM
    *(uint32_t*)(ETM_TRCPRGCTLR) = ETM_TRCPRGCTLR_Enable;
    *(uint32_t*)(ETM_TRCLAR) = ARM_CS_LOCK;
}
 
void tpiu_init(void)
{
    *(uint32_t*)(TPIU_LAR) = ARM_CS_UNLOCK;
    
    *(uint32_t*)(TPIU_CSPSR) = (1 << 3);
    *(uint32_t*)(TPIU_SPPR) = TPIU_SPPR_ParallelMode;
    *(uint32_t*)(TPIU_FFCR) = TPIU_FFCR_EnFCont;
    
    *(uint32_t*)(TPIU_LAR) = ARM_CS_LOCK;
}