1 |
I2S |
Excessive power consumption after using STOP task
|
X |
2 |
NVMC |
CPU code execution from RAM halted during flash page erase operation
|
X |
4 |
GPIO |
Bits in GPIO LATCH register are incorrectly set to 1
|
X |
6 |
POWER |
SLEEPENTER and SLEEPEXIT events asserted after pin reset
|
X |
7 |
KMU |
Subsequent accesses between info_mem and main_mem of the flash may not work properly
|
X |
8 |
SAADC |
Reduced SFDR
|
X |
10 |
LTE Modem |
MAGPIO and MIPI RFFE - high initial voltage
|
X |
12 |
Debug and Trace |
SWD debugger scan
|
X |
14 |
REGULATORS |
Supply regulators default to LDO mode after reset
|
X |
16 |
SAADC |
SAADC result
|
X |
17 |
Debug and Trace |
LTE modem stops when debugging through SWD interface
|
X |
20 |
RAM |
RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode
|
X |
21 |
NVMC |
Disabling instruction cache causes skip of next instruction
|
X |
23 |
UART |
TASKS_RESUME impacts UARTE
|
X |
24 |
NVMC |
CPU is not halted for page erase in debug session
|
X |
26 |
CLOCK, LFXO |
System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
|
X |
28 |
SAADC |
Events are not generated when switching from scan mode to no-scan mode
|
X |
29 |
Debug and Trace |
System reset does not work
|
X |
30 |
PWM |
False SEQEND[0] and SEQEND[1] events are generated
|
X |
31 |
LFXO |
LFXO startup fails
|
X |
32 |
Debug and Trace |
Debug power-up request is not acknowledged
|
X |
33 |
DPPI |
Non-secure code can detect secure events
|
X |