This anomaly applies to IC Rev. Engineering A, build codes SICA-BAA.
The GPIO.LATCH[n] register is unexpectedly set to 1 (Latched).
Set GPIO.PIN_CNF[n].SENSE at low level (3) at the same time as PIN_CNF[n].INPUT is set to Connect (0).
The GPIO.LATCH[n] register is set to 1 (Latched). This could have side effects, depending on how the chip is configured to use this LATCH register.
Always configure PIN_CNF[n].INPUT before PIN_CNF[n].SENSE.