15 |
POWER |
RAM[x].POWERSET/CLR read as zero
|
X |
20 |
RTC |
Register values are invalid
|
X |
36 |
CLOCK |
Some registers are not reset when expected
|
X |
54 |
I2S |
Wrong LRCK polarity in Aligned mode
|
X |
55 |
I2S |
RXPTRUPD and TXPTRUPD events asserted after STOP
|
X |
58 |
SPIM |
An additional byte is clocked out when RXD.MAXCNT = 1
|
X |
66 |
TEMP |
Linearity specification not met with default settings
|
X |
68 |
CLOCK |
EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
|
X |
78 |
TIMER |
High current consumption when using timer STOP task only
|
X |
81 |
GPIO |
PIN_CNF is not retained when in debug interface mode
|
X |
83 |
TWIS |
STOPPED event occurs twice if the STOP task is triggered during a transaction
|
X |
87 |
CPU |
Unexpected wake from System ON Idle when using FPU
|
X |
89 |
GPIOTE |
Static 400 µA current while using GPIOTE
|
X |
94 |
USBD |
BUSSTATE register is not functional
|
X |
96 |
I2S |
DMA buffers can only be located in the first 64 kB of data RAM
|
X |
97 |
GPIOTE |
High current consumption in System ON Idle mode
|
X |
98 |
NFCT |
Not able to communicate with the peer
|
X |
103 |
CCM |
Reset value of CCM.MAXPACKETSIZE causes encryption, decryption, and MIC failures
|
X |
104 |
USBD |
EPDATA event is not always generated
|
X |
110 |
RADIO |
Packet loss or degraded sensitivity
|
X |
111 |
RAM |
Retention in OFF mode is not controlled by RAM[n].POWER->SxRETENTION, but by RAM[n].POWER->SxPOWER
|
X |
112 |
RADIO |
False SFD field matches in IEEE 802.15.4 mode RX
|
X |
113 |
COMP |
Single-ended mode with external reference is not functional
|
X |
115 |
RAM |
RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
|
X |
116 |
NFCT |
HFCLK not stopped when entering into SENSE_FIELD state
|
X |
117 |
System |
Reading address 0x40029618 blocks the device
|
X |
118 |
QSPI |
Reading halfwords or bytes from the XIP region is not supported
|
X |
119 |
POWER |
Wake up from System OFF on VBUS detect is not functional
|
X |
121 |
QSPI |
Second read and long read commands fail
|
X |
122 |
QSPI |
QSPI uses current after being disabled
|
X |
127 |
UARTE |
Two stop bit setting is not functional
|
X |
128 |
PDM |
RATIO register is not functional
|
X |
131 |
UARTE |
EasyDMA transfer size is limited to 255 bytes
|
X |
133 |
CLOCK,RADIO |
NRF_RADIO->EVENTS_BCMATCH event might trigger twice
|
X |
134 |
USBD |
ISOINCONFIG register is not functional
|
X |
135 |
USBD |
SIZE.ISOOUT register does not report empty incoming packets
|
X |
136 |
System |
Bits in RESETREAS are set when they should not be
|
X |
140 |
POWER |
REG0 External circuitry supply in LDO mode is not functional in System ON IDLE
|
X |
142 |
RADIO |
Sensitivity not according to specification
|
X |
143 |
RADIO |
False CRC failures on specific addresses
|
X |
144 |
NFCT |
Not optimal NFC performance
|
X |
145 |
SPIM |
SPIM3 not functional
|
X |
147 |
CLOCK |
LFRC ULP mode not calibrated in production
|
X |
150 |
SAADC |
EVENT_STARTED does not fire
|
X |
151 |
NVMC |
Access to protected memory through Cache
|
X |
153 |
RADIO |
RSSI parameter adjustment
|
X |
154 |
USBD |
USBD acknowledges setup stage without STATUS task
|
X |
155 |
GPIOTE |
IN event may occur more than once on input edge
|
X |
156 |
GPIOTE |
Some CLR tasks give unintentional behavior
|
X |
158 |
RADIO |
High power consumption in DISABLED state
|
X |
160 |
SAADC |
VDDHDIV5 not functional
|
X |
162 |
USBD |
Writing to registers with offset address 0x52C causes USB to halt
|
X |
164 |
RADIO |
Low selectivity in long range mode
|
X |
166 |
USBD |
ISO double buffering not functional
|
X |
170 |
I2S |
NRF_I2S->PSEL CONNECT fields are not readable
|
X |
171 |
USB,USBD |
USB might not power up
|
X |
173 |
GPIO |
Writes to LATCH register take several CPU cycles to take effect
|
X |
176 |
System |
Flash erase through CTRL-AP fails due to watchdog time-out
|
X |
179 |
RTC |
COMPARE event is generated twice from a single RTC compare match
|
X |
180 |
USBD |
Wrong PLL calibration in production
|
X |
181 |
NFCT |
Invalid value in FICR for double-size NFCID1
|
X |
183 |
PWM |
False SEQEND[0] and SEQEND[1] events
|
X |
184 |
NVMC |
Erase or write operations from the external debugger fail when CPU is not halted
|
X |
192 |
CLOCK |
LFRC frequency offset after calibration
|
X |
194 |
I2S |
STOP task does not switch off all resources
|
X |
196 |
I2S |
PSEL acquires GPIOs regardless of ENABLE
|
X |
200 |
USBD |
Cannot write to SIZE.EPOUT register
|
X |
201 |
CLOCK |
EVENTS_HFCLKSTARTED might be generated twice
|
X |