This anomaly applies to IC Rev. Engineering A, build codes QIAA-AA0.
Symptoms
The CPU is interrupted with a bus fault.
Conditions
The CPU reads a halfword or a byte from the XIP region.
The following instructions could cause a byte or halfword load:
- LDRB
- LDRBT
- LDREXB
- LDRSB
- LDRSBT
- LDRH
- LDRHT
- LDREXH
- LDRSH
- LDRSHT
- TBB
- TBH
Consequences
Cannot run code from external memory.
Workaround
Link the firmware such that the run-time location of the read-only data section
is in internal flash or RAM. Also, do not write assembly or C code that reads byte or
halfword sized data from external flash.
- ARM® Compiler armcc
- To prevent the generation of TBB and TBH instructions, use the compiler command line option
--execute_only. This option will also prevent the generation of instructions that read literals from code sections.
- GNU ARM Embedded Toolchain
- Using version Q3 2016 or later, you can prevent the generation of TBB and TBH instructions by using the compiler option
-mpure-code. This option will also prevent the generation of instructions that read literals from the .text section.