[173] GPIO: Writes to LATCH register take several CPU cycles to take effect

This anomaly applies to IC Rev. Engineering A, build codes QIAA-AA0.


A bit in the LATCH register reads '1' even after clearing it by writing '1'.


Reading the LATCH register right after writing to it.


Old value of the LATCH register is read.


Have at least 3 CPU cycles of delay between the write and the subsequent read to the LATCH register. This can be achieved by having 3 dummy reads to the LATCH register.