This section describes the operational states for nRF21540.
When PDN is set to 0, the device is in Power-down state. When PDN is set to 1, the device is activated and enters Program state. All registers contain reset values when the device enters Program state. The device can be set to another state (Receive, Transmit, and UICR Program) using pin control or the SPI interface.
State transitions are controlled by pins PDN, RX_EN, and TX_EN, or bit fields in SPI registers CONFREG0 and CONFREG1. For timings required when switching between operating states, see State transition timing.
When the device is in Receive state, the receive path is active and the transmit path is disabled. In the Receive state, the LNA is enabled.
When the device is in Transmit state, the transmit path is enabled and the receive path is disabled. In Transmit state, the PA is enabled. The device features a configurable TX output power, see TX power control for details.
UICR Program state enables programming to UICR EFUSE (one time programmable memory) of default settings for TX power control. UICR Program state is accessed from Program state by writing specific values to register CONFREG1. Registers CONFREG2 and CONFREG3 are for bit programming definition and triggering UICR EFUSE programming. See UICR programming for more details about UICR programming.
The SPI register interface is described in SPI interface.
| State | Symbol | Description |
|---|---|---|
| Power-down | PD | The device is in Power-down state. |
| Program | PG | The device can be configured and set to other states. |
| UICR program | UICR | User defined initialization values for POUTA_SEL, POUTA_UICR, POUTB_SEL, and POUTB_UICR can be configured to UICR. |
| Receive | RX | The RX path is enabled. |
| Transmit | TX | The TX path is enabled. |