SPI interface

The data transitions for slave in and out (MOSI and MISO) happen on the falling edge of the serial clock (SCK). All SPI transfers are 2 B long.

Input data is sampled on the rising edge of SCK, starting with the first rising edge. The first bit must be stable on the first rising clock edge of SCK. Common definitions for SPI bus are CPOL = 0 and CPHA = 0. In other words, SPI mode 0. The serial data frame is 16 b long and consists of three parts in the following transmission order: command (Cmd), address, and data. All fields are sent on MOSI line MSB first. A write operation consists of a command that is 2 b long, an address of 6 b, followed by 8 b of data. CSN is active low and it is assumed that it is set to 0 at least half an SCK cycle before the first rising edge of SCK. It is then set to logical 1 after half a cycle of the 16th SCK falling edge.

The following commands are used:

• READ, b10 – This command allows reading of registers. The register address to read from is sent after the command. The read data will be clocked out to the MISO line during the data part of the SPI frame.
• WRITE, b11 – This command allows writing to registers. The last 8 b sent on the MOSI line is written to a register pointed with 6-bit address field. The write command has writeback property. When a register is accessed by the write command to update its value, the previous register value will be written to the MISO line in serial format MSB first.

SPI timing specification presents the required timings between CSN signal and SCK edge.

The following figure shows a configuration example for SPI when writing to register CONFREG0. The WRITE command b11 is written to the command field. The first bit on the MOSI line must be set to its value (in this case to 1) before the first rising edge of SCK occurs. This is because Cmd is read on the rising edge of the first and second SCK cycle. SCK rising edges 3 to 8 are used to read the address field, and 9 to 16 read the data field. Register CONFREG0 writeback data is written on the MISO line starting on the falling edge of cycle 8 so that the rising edges of cycle 9 to 16 can be used to read in MISO data on the Master side. Guaranteed settling time for the first read bit before the cycle 9 falling edge can be found in SPI timing specification.

Functionality of the read operation is similar to writeback, meaning that read data is written to the MISO line starting on the cycle 8 falling edge when the read command is given in the Cmd field.

An overview of register address space and accessibility of registers in different operation states is found in SPI timing.

The detailed register map is given in the Register interface.