Electrical specification

The device is calibrated at 25°C to VDD=3.0 V. For other conditions, see Typical characteristics.

Table 1. Current consumption scenarios, common conditions
Condition Value
VDD 3 V
Temperature 25°C
Frequency 2440 MHz
ZL 50 Ω
PIN_TRX 0 dBm

Electrical specification

Current consumption

Symbol Description Min. Typ. Max. Units
IPD

State: PD

45 nA
IPG

State: PG

1.1 mA
IRX

State: RX

2.9 mA
ITX_10dBm

State: TX

POUT = 10 dBm

38 mA
ITX_20dBm

State: TX

POUT = 20 dBm

110 mA

RX

Symbol Description Min. Typ. Max. Units
f

Operating frequency range

2360 2500 MHz
GRX

Gain

13 dB
NFRX

Noise figure

2.7 dB
IMD3-50dBm

Two tone IMD at -50 dBm

Two tone CW, f0: 2440 MHz, f1: +/- 3 MHz, f2: +/- 6 MHz

-109 dBm
IMD3-30dBm

Two tone IMD at -30 dBm

Two tone CW, f0: 2440 MHz, f1: +/- 3 MHz, f2: +/- 6 MHz

-75 dBm
H2RX

Harmonic 2nd (CW, -10 dBm)

-20 dBm
H3RX

Harmonic 3rd (CW, -10 dBm)

-17 dBm
S11_ANTdB

ANT port input reflection (over input frequency, 50 Ω)

-7 dB
S22_TRXdB

TRX port output reflection (over input frequency, 50 Ω)

-12.0 dB
PMAX,RX

Maximum output power (at TRX, PIN = 0 dBm)

2.5 5.0 dBm

TX

Symbol Description Min. Typ. Max. Units
f

Operating frequency range

2360 2500 MHz
PSAT

Saturated output power; GFSK/OQPSK modulation

21.5 dBm
GTX

Power Gain

20 dB
Tcarrier

Carrier switching time

POUT from -30 dBm to +20 dBm

1 µs
PSPUR2MHz

In-band spurious emissions 2 MHz (GFSK/OQPSK)

-26 dBm
PSPUR3MHz

In-band spurious emissions 3 MHz (GFSK/OQPSK)

-36 dBm
H2, H3

Harmonic, 2nd, 3rd; RBW = 1.0 MHz

-42 dBm
S11_TRXdB

Input reflection at TRX pin (over input frequency range, 50 Ω)

-10 dB
VSWRSTB

Unconditionally stable

-
VSWRRGN

No permanent damage (load 10:1, all phase angles)

-
PAE

Power Added Efficiency

32 %

SPI timing specification

Symbol Description Min. Typ. Max. Units
TSPI,START

Minimum time from PDN high to SPI is ready to receive data

17.5 µs
TSCK

SCK clock period (50% duty cycle)

112 125 ns
TCSN-SCK1

CSN lead time

Time from CSN set to 0 to first rising edge at SCK

62.5 ns
TSCK16-CSN

CSN trail time

Time from 16th falling edge at SCK to CSN set to 1

62.5 ns
TCSN

CSN idle time

Time required between consecutive transmissions

125 ns
TS_MISO

MISO settling time

Guaranteed settling margin for MISO before 9th rising edge at SCK

30 ns

Typical characteristics

The following figure shows the TX output power control behavior for typical conditions.

Figure 1. TX gain control behavior
TX gain behavior

The following figure shows the relationship between TX gain and current consumption.

Figure 2. TX gain and current consumption
TX gain behavior

The following figure shows the TX gain over operating frequency for typical conditions, with register CONFREG0.TX_GAIN=POUTA_PROD (20 dB).

Figure 3. TX gain over operating frequency 20 dB
TX gain behavior

The following figure shows the TX gain over operating frequency for typical conditions, with register CONFREG0.TX_GAIN=POUTB_PROD (10 dB).

Figure 4. TX gain over operating frequency 10 dB
TX gain behavior

The following figure shows the TX gain over operating temperature, with register CONFREG0.TX_GAIN=POUTA_PROD (20 dB).

Figure 5. TX gain over temperature 20 dB
TX gain behavior

The following figure shows the TX gain over operating temperature, with register CONFREG0.TX_GAIN=POUTB_PROD (10 dB).

Figure 6. TX gain over temperature 10 dB
TX gain behavior

The following figure shows the TX gain over VDD, with register CONFREG0.TX_GAIN=POUTA_PROD (20 dB).

Figure 7. TX gain over VDD 20 dB
TX gain behavior

The following figure shows the TX gain over VDD, with register CONFREG0.TX_GAIN=POUTB_PROD (10 dB).

Figure 8. TX gain over VDD 10 dB
TX gain behavior

The following figure shows the RX gain over the operating frequency.

Figure 9. RX gain over operating frequency
RX gain behavior

The following figure shows the RX gain over temperature.

Figure 10. RX gain over temperature
RX gain behavior

The following figure shows the RX gain over VDD.

Figure 11. RX gain over VDD
RX gain behavior