Settling time requirements when switching between operational states are defined in the following table.
When using SPI control, the maximum settling time is defined from the falling edge of SPI clock cycle 16. For more details on SPI, see SPI interface.
Note: GPIO control is faster than SPI control.
| Symbol | Parameter | Note | Max. | Unit |
|---|---|---|---|---|
| TTRX→PD | Settling time from states TX or RX to PD | Triggered by PDN | 10 | µs |
| TPD→PG | Settling time from state PD to PG | Triggered by PDN | 17.5 | µs |
| TPG→TRX | Settling time from state PG to TX or RX | Triggered by RX_EN, TX_EN, or through SPI register control | 10.5 | µs |
| TTRX→PG | Power-off time when changing from RX or TX to PG | Triggered by RX_EN, TX_EN, or through SPI register control | 3 | µs |
| TPG→PD | Settling time from state PG to PD | Triggered by PDN | 10 | µs |
An example of RX timing using an RX_EN pin-based configuration is shown in the following figure.
Figure 1. Pin control RX state
The following figure shows the Receive state configured using SPI.
Figure 2. SPI control RX state
The following figure shows the Transmit state configured through pin.
Figure 3. Pin control TX state
The following figure shows the Transmit state configured using SPI.
Figure 4. SPI control TX state
