Macros | |
| #define | NRFX_UARTE_TX_BLOCKING NRFX_BIT(0) |
| Flag indicating blocking transfer. | |
| #define | NRFX_UARTE_TX_EARLY_RETURN NRFX_BIT(1) |
| Flag indicating to return from blocking transfer not waiting for the last transmit event. | |
| #define | NRFX_UARTE_TX_LINK NRFX_BIT(2) |
| Flag indicating that the nrfx_uarte_tx call will be linked to an active transfer. | |
Flags apply only if an instance is initialized with a user handler. Otherwise flags are ignored and all transfers are blocking.
| #define NRFX_UARTE_TX_BLOCKING NRFX_BIT(0) |
Flag indicating blocking transfer.
When the flag is set, the transfer is synchronous even if the driver is configured to non-blocking operation. If UARTE is transmitting when the user requests blocking transfer, NRFX_ERROR_BUSY is returned. A driver state is determined by hardware, thus it is accepted to poll the driver and continuously request blocking transfer until it is accepted. It can be done from any priority context. Blocking transfer returns when the buffer is transferred or when the user buffer is no longer in use (see NRFX_UARTE_TX_EARLY_RETURN).
| #define NRFX_UARTE_TX_EARLY_RETURN NRFX_BIT(1) |
Flag indicating to return from blocking transfer not waiting for the last transmit event.
The flag indicates a blocking transfer just like NRFX_UARTE_TX_BLOCKING. However, when the flag is set, if the transfer is still ongoing and if the transfer of the last byte already has started, nrfx_uarte_tx returns instead of waiting for the transfer to end.
| #define NRFX_UARTE_TX_LINK NRFX_BIT(2) |
Flag indicating that the nrfx_uarte_tx call will be linked to an active transfer.
UARTE DMA registers are buffered which means that once transfer is started, registers with transfer details (pointer and length) can be overwritten. If that is combined with the (D)PPI connection between ENDTX and STARTTX events, then two transfers are linked together and bytes are transferred without any gap allowing to utilize the maximum bandwidth.
When the flag is set, it indicates that the user can set up an ENDTX-STARTTX (D)PPI connection and wants to perform linked transfers. It is the user's responsibility to disable the (D)PPI connection when the last transfer is started. If the user does not set up an ENDTX-STARTTX (D)PPI connection, then the transfer is restarted from the context of ENDTX event handling which is earlier than context of the NRFX_UARTE_EVT_TX_DONE. The flag has no impact if used while there is no ongoing transfer.
For example, if a sequence consists of three transfers, then the first nrfx_uarte_tx can be called with or without the flag and the following two transfers must have the flag set. The second nrfx_uarte_tx can be called immediately after the first one and the third one after the first NRFX_UARTE_EVT_TX_DONE event. After the second NRFX_UARTE_EVT_TX_DONE event is received, the (D)PPI connection must be disabled (if it was used).
When (D)PPI connection is used, then it is critical that (D)PPI connection is disabled on time, before the last transfer is completed. Otherwise, the transfer will be repeated, and unwanted data will be transferred. Hence, it is recommended to use longer buffers. Time needed to send the buffer must be longer than the maximum system latency.
When the flag is used, then the driver instance must not use the ENDTX-STOPTX (D)PPI connection.
When linked transfers are used, then blocking transfers (see NRFX_UARTE_TX_BLOCKING and NRFX_UARTE_TX_EARLY_RETURN) cannot be performed. An error is returned when the flag is set and the nrfx_uarte_tx is called during ongoing blocking transfer.