Macros | |
#define | NRFX_UARTE_RX_ENABLE_CONT NRFX_BIT(0) |
Flag for configuring continuous reception. | |
#define | NRFX_UARTE_RX_ENABLE_STOP_ON_END NRFX_BIT(1) |
Flag indicating that receiver is stopped when new buffer is not provided. | |
#define | NRFX_UARTE_RX_ENABLE_KEEP_FIFO_CONTENT NRFX_BIT(2) |
Flag indicating that FIFO content that was flushed after the last stopping shall be kept. | |
#define NRFX_UARTE_RX_ENABLE_CONT NRFX_BIT(0) |
Flag for configuring continuous reception.
When the flag is set, the ENDRX event is shortened with the STARTRX task. The flag should not be used together with short buffers in case there is a risk that a new buffer is not provided on time. If the flag is set and a new buffer is not provided on time, a receiver starts to overwrite the current buffer. If not set and a new buffer has been provided on time, a new transfer will be triggered from the ENDRX interrupt handler. This flag is recommended to be used with longer buffers to ensure lossless reception without HWFC detection.
#define NRFX_UARTE_RX_ENABLE_KEEP_FIFO_CONTENT NRFX_BIT(2) |
Flag indicating that FIFO content that was flushed after the last stopping shall be kept.
When a receiver is stopped, it is possible that there is some data in the hardware FIFO that was not stored in the user buffer due to the lack of capacity. As a result, that data is flushed to an internal buffer. If the flag is set, the flushed data is kept and copied into the user buffer.
Using the flag makes the user to provide their buffer for flushed data during the initialization.
#define NRFX_UARTE_RX_ENABLE_STOP_ON_END NRFX_BIT(1) |
Flag indicating that receiver is stopped when new buffer is not provided.
Setting a flag changes the behavior of the UARTE driver when receiving to the buffer is completed and a new buffer is not provided. When the flag is set, stopping is initiated. Since the stopping takes time, this operation can still be revoked by providing a new buffer (nrfx_uarte_rx_buffer_set). When the flag is not set, then the receiver is kept enabled, and incoming data is put in the hardware FIFO (if HWFC is disabled) until FIFO is full and bytes are dropped.