POWER — Power supply

This device has the following power supply features:

Note: Two additional external passive components are required to use the DC/DC regulator.

Regulators

The following internal power regulator alternatives are supported:
  • Internal LDO regulator
  • Internal DC/DC regulator

The LDO is the default regulator.

The DC/DC regulator can be used as an alternative to the LDO regulator and is enabled through the DCDCEN register. Using the DC/DC regulator will reduce current consumption compared to when using the LDO regulator, but the DC/DC regulator requires an external LC filter to be connected, as shown in Figure 2.

Figure 1. LDO regulator setup

Figure 2. DC/DC regulator setup

System OFF mode

System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core functionality is powered down and all ongoing tasks are terminated.

The device can be put into System OFF mode using the POWER register interface. When in System OFF mode, the device can be woken up through one of the following signals:

  1. The DETECT signal, optionally generated by the GPIO peripheral
  2. The ANADETECT signal, optionally generated by the LPCOMP module
  3. The SENSE signal, optionally generated by the NFC module to “wake-on-field”
  4. A reset

When the system wakes up from System OFF mode, it gets reset. For more details, see Reset behavior.

One or more RAM sections can be retained in System OFF mode depending on the settings in the RAM[n].POWER registers.

RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually overwritten by the startup code provided with the nRF application examples.

Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have been completed. This is usually accomplished by making sure that the EasyDMA enabled peripheral is not active when entering System OFF.

Emulated System OFF mode

If the device is in debug interface mode, System OFF will be emulated to secure that all required resources needed for debugging are available during System OFF.

See Debug and trace for more information. Required resources needed for debugging include the following key components: Debug and trace, CLOCK — Clock control, POWER — Power supply, NVMC — Non-volatile memory controller, CPU, Flash, and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be executed.

System ON mode

System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or peripherals, can be in IDLE or RUN mode, depending on the configuration set by the software and the state of the application executing.

Register RESETREAS provides information about the source that caused the wakeup or reset.

The system can switch on and off the appropriate internal power sources, depending on how much power is needed at any given time. The power requirement of a peripheral is directly related to its activity level, and the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or events are generated.

Sub power modes

In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in one of the two sub power modes.

The sub power modes are:

  • Constant latency
  • Low power

In constant latency mode the CPU wakeup latency and the PPI task response will be constant and kept at a minimum. This is secured by forcing a set of base resources on while in sleep. The advantage of having a constant and predictable latency will be at the cost of having increased power consumption. The constant latency mode is selected by triggering the CONSTLAT task.

In low power mode the automatic power management system, described in System ON mode, ensures the most efficient supply option is chosen to save the most power. The advantage of having the lowest power possible will be at the cost of having varying CPU wakeup latency and PPI task response. The low power mode is selected by triggering the LOWPWR task.

When the system enters System ON mode, it will, by default, reside in the low power sub-power mode.

Power supply supervisor

The power supply supervisor initializes the system at power-on and provides an early warning of impending power failure.

In addition, the power supply supervisor puts the system in a reset state if the supply voltage is too low for safe operation (brownout). The power supply supervisor is illustrated in Figure 3.

Figure 3. Power supply supervisor

Power-fail comparator

The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It will not reset the system, but give the CPU time to prepare for an orderly power-down.

The comparator features a hysteresis of VHYST, as illustrated in Figure 4. The threshold VPOF is set in register POFCON. If the POF is enabled and the supply voltage falls below VPOF, the POFWARN event will be generated. This event will also be generated if the supply voltage is already below VPOF at the time the POF is enabled, or if VPOF is re-configured to a level above the supply voltage.

If power-fail warning is enabled and the supply voltage is below VPOF the power-fail comparator will prevent the NVMC from performing write operations to the NVM. See NVMC — Non-volatile memory controller for more information about the NVMC.

Figure 4. Power-fail comparator (BOR = Brownout reset)

To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not running.

RAM sections

RAM section power control is used for retention in System OFF mode and for powering down unused sections in System ON mode.

Each RAM section can power up and down independently in both System ON and System OFF mode. See chapter Memory for more information on RAM sections.

Reset

There are multiple sources that may trigger a reset.

After a reset has occurred, register RESETREAS can be read to determine which source generated the reset.

Power-on reset

The power-on reset generator initializes the system at power-on.

The system is held in reset state until the supply has reached the minimum operating voltage and the internal voltage regulators have started.

A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply range, may result in a system reset.

Pin reset

A pin reset is generated when the physical reset pin on the device is asserted.

Pin reset is configured via the PSELRESET[0] and PSELRESET[1] registers.

Note: Pin reset is not available on all pins.

Wakeup from System OFF mode reset

The device is reset when it wakes up from System OFF mode.

The DAP is not reset following a wake up from System OFF mode if the device is in debug interface mode. Refer to chapter Debug and trace for more information.

Soft reset

A soft reset is generated when the SYSRESETREQ bit of the Application Interrupt and Reset Control Register (AIRCR register) in the ARM® core is set.

Refer to ARM documentation for more details.

A soft reset can also be generated via the RESET register in the CTRL-AP.

Watchdog reset

A Watchdog reset is generated when the watchdog times out.

Refer to chapter WDT — Watchdog timer for more information.

Brown-out reset

The brown-out reset generator puts the system in reset state if the supply voltage drops below the brownout reset (BOR) threshold.

Refer to section Power fail comparator for more information.

Retained registers

A retained register is a register that will retain its value in System OFF mode and through a reset, depending on reset source. See individual peripheral chapters for information of which registers are retained for the various peripherals.

Reset behavior

Reset source Reset target
CPU Peripherals GPIO Debuga SWJ-DP RAM WDT Retained registers RESETREAS
CPU lockup 2 x x x            
Soft reset x x x            
Wakeup from System OFF mode reset x x   x 3   x 4      
Watchdog reset 5 x x x x   x x x  
Pin reset x x x x   x x x  
Brownout reset x x x x x x x x x
Power on reset x x x x x x x x x
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x40000000 POWER POWER

Power control

   
Table 2. Register Overview
Register Offset Description
TASKS_CONSTLAT 0x078

Enable constant latency mode

 
TASKS_LOWPWR 0x07C

Enable low power mode (variable latency)

 
EVENTS_POFWARN 0x108

Power failure warning

 
EVENTS_SLEEPENTER 0x114

CPU entered WFI/WFE sleep

 
EVENTS_SLEEPEXIT 0x118

CPU exited WFI/WFE sleep

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
RESETREAS 0x400

Reset reason

 
RAMSTATUS 0x428

RAM status register

Deprecated

SYSTEMOFF 0x500

System OFF register

 
POFCON 0x510

Power failure comparator configuration

 
GPREGRET 0x51C

General purpose retention register

 
GPREGRET2 0x520

General purpose retention register

 
RAMON 0x524

RAM on/off register (this register is retained)

Deprecated

RAMONB 0x554

RAM on/off register (this register is retained)

Deprecated

DCDCEN 0x578

DC/DC enable register

 
RAM[0].POWER 0x900

RAM0 power control register

 
RAM[0].POWERSET 0x904

RAM0 power control set register

 
RAM[0].POWERCLR 0x908

RAM0 power control clear register

 
RAM[1].POWER 0x910

RAM1 power control register

 
RAM[1].POWERSET 0x914

RAM1 power control set register

 
RAM[1].POWERCLR 0x918

RAM1 power control clear register

 
RAM[2].POWER 0x920

RAM2 power control register

 
RAM[2].POWERSET 0x924

RAM2 power control set register

 
RAM[2].POWERCLR 0x928

RAM2 power control clear register

 
RAM[3].POWER 0x930

RAM3 power control register

 
RAM[3].POWERSET 0x934

RAM3 power control set register

 
RAM[3].POWERCLR 0x938

RAM3 power control clear register

 
RAM[4].POWER 0x940

RAM4 power control register

 
RAM[4].POWERSET 0x944

RAM4 power control set register

 
RAM[4].POWERCLR 0x948

RAM4 power control clear register

 
RAM[5].POWER 0x950

RAM5 power control register

 
RAM[5].POWERSET 0x954

RAM5 power control set register

 
RAM[5].POWERCLR 0x958

RAM5 power control clear register

 
RAM[6].POWER 0x960

RAM6 power control register

 
RAM[6].POWERSET 0x964

RAM6 power control set register

 
RAM[6].POWERCLR 0x968

RAM6 power control clear register

 
RAM[7].POWER 0x970

RAM7 power control register

 
RAM[7].POWERSET 0x974

RAM7 power control set register

 
RAM[7].POWERCLR 0x978

RAM7 power control clear register

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                  

C

B

   

A

   
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

POFWARN

   

Write '1' to Enable interrupt for POFWARN event

See EVENTS_POFWARN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

SLEEPENTER

   

Write '1' to Enable interrupt for SLEEPENTER event

See EVENTS_SLEEPENTER

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

   

Write '1' to Enable interrupt for SLEEPEXIT event

See EVENTS_SLEEPEXIT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                  

C

B

   

A

   
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

POFWARN

   

Write '1' to Disable interrupt for POFWARN event

See EVENTS_POFWARN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

SLEEPENTER

   

Write '1' to Disable interrupt for SLEEPENTER event

See EVENTS_SLEEPENTER

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

   

Write '1' to Disable interrupt for SLEEPEXIT event

See EVENTS_SLEEPEXIT

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

RESETREAS

Address offset: 0x400

Reset reason

Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on-reset or a brownout reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                        

H

G

F

E

                       

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

RESETPIN

   

Reset from pin-reset detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

B RW

DOG

   

Reset from watchdog detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

C RW

SREQ

   

Reset from soft reset detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

D RW

LOCKUP

   

Reset from CPU lock-up detected

     

NotDetected

0

Not detected

     

Detected

1

Detected

E RW

OFF

   

Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO

     

NotDetected

0

Not detected

     

Detected

1

Detected

F RW

LPCOMP

   

Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP

     

NotDetected

0

Not detected

     

Detected

1

Detected

G RW

DIF

   

Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode

     

NotDetected

0

Not detected

     

Detected

1

Detected

H RW

NFC

   

Reset due to wake up from System OFF mode by NFC field detect

     

NotDetected

0

Not detected

     

Detected

1

Detected

 

RAMSTATUS ( Deprecated )

Address offset: 0x428

RAM status register

Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0 and RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any of the RAM sections associated with a block are on.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                        

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RAMBLOCK0

   

RAM block 0 is on or off/powering up

     

Off

0

Off

     

On

1

On

B R

RAMBLOCK1

   

RAM block 1 is on or off/powering up

     

Off

0

Off

     

On

1

On

C R

RAMBLOCK2

   

RAM block 2 is on or off/powering up

     

Off

0

Off

     

On

1

On

D R

RAMBLOCK3

   

RAM block 3 is on or off/powering up

     

Off

0

Off

     

On

1

On

 

SYSTEMOFF

Address offset: 0x500

System OFF register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A W

SYSTEMOFF

   

Enable System OFF mode

     

Enter

1

Enable System OFF mode

 

POFCON

Address offset: 0x510

Power failure comparator configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                    

B

B

B

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

POF

   

Enable or disable power failure comparator

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

THRESHOLD

   

Power failure comparator threshold setting

     

V17

4

Set threshold to 1.7 V

     

V18

5

Set threshold to 1.8 V

     

V19

6

Set threshold to 1.9 V

     

V20

7

Set threshold to 2.0 V

     

V21

8

Set threshold to 2.1 V

     

V22

9

Set threshold to 2.2 V

     

V23

10

Set threshold to 2.3 V

     

V24

11

Set threshold to 2.4 V

     

V25

12

Set threshold to 2.5 V

     

V26

13

Set threshold to 2.6 V

     

V27

14

Set threshold to 2.7 V

     

V28

15

Set threshold to 2.8 V

 

GPREGRET

Address offset: 0x51C

General purpose retention register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

GPREGRET

   

General purpose retention register

This register is a retained register

 

GPREGRET2

Address offset: 0x520

General purpose retention register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

GPREGRET

   

General purpose retention register

This register is a retained register

 

RAMON ( Deprecated )

Address offset: 0x524

RAM on/off register (this register is retained)

Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to a block comprising RAM0.S0 and RAM0.S1 and RAM block 1 is equivalent to a block comprising RAM1.S0 and RAM1.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling registers instead.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x00000003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Id RW Field Value Id Value Description
A RW

ONRAM0

   

Keep RAM block 0 on or off in system ON Mode

     

RAM0Off

0

Off

     

RAM0On

1

On

B RW

ONRAM1

   

Keep RAM block 1 on or off in system ON Mode

     

RAM1Off

0

Off

     

RAM1On

1

On

C RW

OFFRAM0

   

Keep retention on RAM block 0 when RAM block is switched off

     

RAM0Off

0

Off

     

RAM0On

1

On

D RW

OFFRAM1

   

Keep retention on RAM block 1 when RAM block is switched off

     

RAM1Off

0

Off

     

RAM1On

1

On

 

RAMONB ( Deprecated )

Address offset: 0x554

RAM on/off register (this register is retained)

Since this register is deprecated the following substitutions have been made: RAM block 2 is equivalent to a block comprising RAM2.S0 and RAM2.S1 and RAM block 3 is equivalent to a block comprising RAM3.S0 and RAM3.S1. For new designs it is recommended to use the POWER.RAM-0.POWER and its sibling registers instead.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x00000003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Id RW Field Value Id Value Description
A RW

ONRAM2

   

Keep RAM block 2 on or off in system ON Mode

     

RAM2Off

0

Off

     

RAM2On

1

On

B RW

ONRAM3

   

Keep RAM block 3 on or off in system ON Mode

     

RAM3Off

0

Off

     

RAM3On

1

On

C RW

OFFRAM2

   

Keep retention on RAM block 2 when RAM block is switched off

     

RAM2Off

0

Off

     

RAM2On

1

On

D RW

OFFRAM3

   

Keep retention on RAM block 3 when RAM block is switched off

     

RAM3Off

0

Off

     

RAM3On

1

On

 

DCDCEN

Address offset: 0x578

DC/DC enable register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

DCDCEN

   

Enable or disable DC/DC converter

     

Disabled

0

Disable

     

Enabled

1

Enable

 

RAM[0].POWER

Address offset: 0x900

RAM0 power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A RW

S0POWER

   

Keep RAM section S0 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

B RW

S1POWER

   

Keep RAM section S1 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S1RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

C RW

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

D RW

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

 

RAM[0].POWERSET

Address offset: 0x904

RAM0 power control set register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM0 on or off in System ON mode

     

On

1

On

B W

S1POWER

   

Keep RAM section S1 of RAM0 on or off in System ON mode

     

On

1

On

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

On

1

On

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

On

1

On

 

RAM[0].POWERCLR

Address offset: 0x908

RAM0 power control clear register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM0 on or off in System ON mode

     

Off

1

Off

B W

S1POWER

   

Keep RAM section S1 of RAM0 on or off in System ON mode

     

Off

1

Off

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

Off

1

Off

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

Off

1

Off

 

RAM[1].POWER

Address offset: 0x910

RAM1 power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A RW

S0POWER

   

Keep RAM section S0 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

B RW

S1POWER

   

Keep RAM section S1 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S1RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

C RW

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

D RW

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

 

RAM[1].POWERSET

Address offset: 0x914

RAM1 power control set register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM1 on or off in System ON mode

     

On

1

On

B W

S1POWER

   

Keep RAM section S1 of RAM1 on or off in System ON mode

     

On

1

On

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

On

1

On

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

On

1

On

 

RAM[1].POWERCLR

Address offset: 0x918

RAM1 power control clear register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM1 on or off in System ON mode

     

Off

1

Off

B W

S1POWER

   

Keep RAM section S1 of RAM1 on or off in System ON mode

     

Off

1

Off

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

Off

1

Off

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

Off

1

Off

 

RAM[2].POWER

Address offset: 0x920

RAM2 power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A RW

S0POWER

   

Keep RAM section S0 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

B RW

S1POWER

   

Keep RAM section S1 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S1RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

C RW

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

D RW

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

 

RAM[2].POWERSET

Address offset: 0x924

RAM2 power control set register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM2 on or off in System ON mode

     

On

1

On

B W

S1POWER

   

Keep RAM section S1 of RAM2 on or off in System ON mode

     

On

1

On

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

On

1

On

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

On

1

On

 

RAM[2].POWERCLR

Address offset: 0x928

RAM2 power control clear register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM2 on or off in System ON mode

     

Off

1

Off

B W

S1POWER

   

Keep RAM section S1 of RAM2 on or off in System ON mode

     

Off

1

Off

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

Off

1

Off

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

Off

1

Off

 

RAM[3].POWER

Address offset: 0x930

RAM3 power control register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A RW

S0POWER

   

Keep RAM section S0 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

B RW

S1POWER

   

Keep RAM section S1 ON or OFF in System ON mode.

RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S1RETENTION. All RAM sections will be OFF in System OFF mode.

     

Off

0

Off

     

On

1

On

C RW

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

D RW

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is in OFF

     

Off

0

Off

     

On

1

On

 

RAM[3].POWERSET

Address offset: 0x934

RAM3 power control set register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
A W

S0POWER

   

Keep RAM section S0 of RAM3 on or off in System ON mode

     

On

1

On

B W

S1POWER

   

Keep RAM section S1 of RAM3 on or off in System ON mode

     

On

1

On

C W

S0RETENTION

   

Keep retention on RAM section S0 when RAM section is switched off

     

On

1

On

D W

S1RETENTION

   

Keep retention on RAM section S1 when RAM section is switched off

     

On

1

On

 

RAM[3].POWERCLR

Address offset: 0x938

RAM3 power control clear register

When read, this register will return the value of the POWER register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                            

D

C

                           

B

A

Reset 0x0000FFFF 0