NVMC — Non-volatile memory controller

The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and the UICR.

Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so may result in unpredictable behavior.

Writing to Flash

When writing is enabled, the Flash is written by writing a full 32-bit word to a word-aligned address in the Flash.

The NVMC is only able to write '0' to bits in the Flash that are erased, that is, set to '1'. It cannot write back a bit to '1'.

As illustrated in Memory, the Flash is divided into multiple pages that are further divided into multiple blocks. The same block in the Flash can only be written nWRITE number of times before an erase must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory for block size.

Only full 32-bit words can be written to Flash using the NVMC interface. To write less than 32 bits to Flash, write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the restriction about the number of writes (see above) still applies in this case.

The time it takes to write a word to the Flash is specified by tWRITE. The CPU is halted while the NVMC is writing to the Flash.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

Erasing a page in Flash

When erase is enabled, the Flash can be erased page by page using the ERASEPAGE register.

After erasing a Flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by tERASEPAGE. The CPU is halted while the NVMC performs the erase operation.

Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as Flash. After UICR has been written, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or ERASEALL.

The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted while the NVMC is writing to the UICR.

Erasing user information configuration registers (UICR)

When erase is enabled, UICR can be erased using the ERASEUICR register.

After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE. The CPU is halted while the NVMC performs the erase operation.

Erase all

When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL register. ERASEALL will not erase the factory information configuration registers (FICR).

The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted while the NVMC performs the erase operation.

Cache

An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

See the Memory map in Memory map for the location of Flash.

A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states for a cache miss, where the instruction is not available in the cache and needs to be fetched from Flash, depends on the processor frequency and is shown in CPU

Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will reduce.

When disabled, the cache does not use current and does not retain its content.

It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC

Non-Volatile Memory Controller

   
Table 2. Register Overview
Register Offset Description
READY 0x400

Ready flag

 
CONFIG 0x504

Configuration register

 
ERASEPAGE 0x508

Register for erasing a page in Code area

 
ERASEPCR1 0x508

Register for erasing a page in Code area. Equivalent to ERASEPAGE.

Deprecated

ERASEALL 0x50C

Register for erasing all non-volatile user memory

 
ERASEPCR0 0x510

Register for erasing a page in Code area. Equivalent to ERASEPAGE.

Deprecated

ERASEUICR 0x514

Register for erasing User Information Configuration Registers

 
ICACHECNF 0x540

I-Code cache configuration register.

 
IHIT 0x548

I-Code cache hit counter.

 
IMISS 0x54C

I-Code cache miss counter.

 

READY

Address offset: 0x400

Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

READY

   

NVMC is ready or busy

     

Busy

0

NVMC is busy (on-going write or erase operation)

     

Ready

1

NVMC is ready

 

CONFIG

Address offset: 0x504

Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

WEN

   

Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.

     

Ren

0

Read only access

     

Wen

1

Write Enabled

     

Een

2

Erase enabled

 

ERASEPAGE

Address offset: 0x508

Register for erasing a page in Code area

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ERASEPAGE

   

Register for starting erase of a page in Code area

The value is the address to the page to be erased. (Addresses of first word in page). Note that code erase has to be enabled by CONFIG.EEN before the page can be erased. Attempts to erase pages that are outside the code area may result in undesirable behaviour, e.g. the wrong page may be erased.

 

ERASEPCR1 ( Deprecated )

Address offset: 0x508

Register for erasing a page in Code area. Equivalent to ERASEPAGE.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ERASEPCR1

   

Register for erasing a page in Code area. Equivalent to ERASEPAGE.

 

ERASEALL

Address offset: 0x50C

Register for erasing all non-volatile user memory

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ERASEALL

   

Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.

     

NoOperation

0

No operation

     

Erase

1

Start chip erase

 

ERASEPCR0 ( Deprecated )

Address offset: 0x510

Register for erasing a page in Code area. Equivalent to ERASEPAGE.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ERASEPCR0

   

Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.

 

ERASEUICR

Address offset: 0x514

Register for erasing User Information Configuration Registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ERASEUICR

   

Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.

     

NoOperation

0

No operation

     

Erase

1

Start erase of UICR

 

ICACHECNF

Address offset: 0x540

I-Code cache configuration register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                               B               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

CACHEEN

   

Cache enable

     

Disabled

0

Disable cache. Invalidates all cache entries.

     

Enabled

1

Enable cache

B RW

CACHEPROFEN

   

Cache profiling enable

     

Disabled

0

Disable cache profiling

     

Enabled

1

Enable cache profiling

 

IHIT

Address offset: 0x548

I-Code cache hit counter.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

HITS

   

Number of cache hits

 

IMISS

Address offset: 0x54C

I-Code cache miss counter.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MISSES

   

Number of cache misses

 

Electrical specification

Flash programming

Symbol Description Min. Typ. Max. Units
nWRITE,BLOCK

Amount of writes allowed in a block between erase

181  
tWRITE

Time to write one word

67.5 338 µs
tERASEPAGE

Time to erase one page

2.05 89.7 ms
tERASEALL

Time to erase all flash

6.72 295.3 ms

Cache size

Symbol Description Min. Typ. Max. Units
SizeICODE

I-Code cache size

2048 Bytes

Documentation feedback | Developer Zone | Updated 2017-02-09